公开(公告)号：US07965213B1

公开(公告)日：2011-06-21

申请号：US12717910

申请日：2010-03-04

申请人： Chang-Shun Liu ,  Tse-Chi Lin ,  Yu-Hsuan Tu ,  Kang-Wei Hsueh

发明人： Chang-Shun Liu ,  Tse-Chi Lin ,  Yu-Hsuan Tu ,  Kang-Wei Hsueh

IPC分类号： H03M1/66

CPC分类号： H03M1/0665 ,  H03M1/74

摘要： An element-selecting method is utilized for selecting the converting elements of the DAC to perform the digital-to-analog conversion. The element-selecting method first determines whether the selected times of the converting elements are all equal or not. When the selected times of the converting elements are all equal, the element-selecting method determines a shifting-step according to the input signal and the number of the converting elements; otherwise, the element-selecting method determines the shifting-step to be a predetermined value. The element-selecting method then selects a converting element from the DAC by means of separating the converting element from a last selected converting element by the shifting-step. In this way, the error accumulated because of the mismatch of the converting elements is eliminated, and the toggle rate of the DAC is reduced. Hence, the glitch and the dynamic errors of the DAC are reduced, improving the performance of the DAC.

摘要翻译： 元件选择方法用于选择DAC的转换元件以进行数模转换。 元素选择方法首先确定转换元素的所选择的时间是否全部相等。 当转换元件的所选择的时间全部相等时，元件选择方法根据输入信号和转换元件的数量确定移位步长; 否则，元件选择方法将移位步骤确定为预定值。 然后，元素选择方法通过借助于通过移位步骤将转换元件与最后选择的转换元件分离，从DAC中选择转换元件。 以这种方式，消除了由于转换元件不匹配而累积的误差，并且DAC的切换速率降低。 因此，减小了DAC的毛刺和动态误差，提高了DAC的性能。

公开(公告)号：US07948414B2

公开(公告)日：2011-05-24

申请号：US12538153

申请日：2009-08-09

申请人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

发明人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

IPC分类号： H03M3/00

CPC分类号： H03M3/424 ,  H03M3/454

摘要： A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

摘要翻译： 用于接收模拟输入信号以产生数字输出信号的Δ-Σ模数转换装置包括减法单元，量化器和反馈单元。 减法单元用于执行减法函数以根据模拟输入信号和反馈信号产生减去的信号。 量化器耦合到减法单元，用于执行量化，以根据减法信号产生量化信号。 反馈单元耦合在减法单元和量化器之间，用于根据量化信号向减法单元提供反馈信号。 减法单元布置成减小量化器的信号输入摆幅。

公开(公告)号：US08212702B2

公开(公告)日：2012-07-03

申请号：US13087386

申请日：2011-04-15

申请人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

发明人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

IPC分类号： H03M3/00

CPC分类号： H03M3/424 ,  H03M3/454

摘要： A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

摘要翻译： 用于接收模拟输入信号以产生数字输出信号的Δ-Σ模数转换装置包括减法单元，量化器和反馈单元。 减法单元用于执行减法函数以根据模拟输入信号和反馈信号产生减去的信号。 量化器耦合到减法单元，用于执行量化，以根据减法信号产生量化信号。 反馈单元耦合在减法单元和量化器之间，用于根据量化信号向减法单元提供反馈信号。 减法单元布置成减小量化器的信号输入摆幅。

公开(公告)号：US20110187571A1

公开(公告)日：2011-08-04

申请号：US13087386

申请日：2011-04-15

申请人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

发明人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

IPC分类号： H03M3/02

CPC分类号： H03M3/424 ,  H03M3/454

摘要： A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

公开(公告)号：US20110032132A1

公开(公告)日：2011-02-10

申请号：US12538153

申请日：2009-08-09

申请人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

发明人： Tse-Chi Lin ,  Yu-Hsuan Tu ,  Chang-Shun Liu ,  Kang-Wei Hsueh

IPC分类号： H03M3/00 ,  H03M1/12

CPC分类号： H03M3/424 ,  H03M3/454

摘要： A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

摘要翻译： 用于接收模拟输入信号以产生数字输出信号的Δ-Σ模数转换装置包括减法单元，量化器和反馈单元。 减法单元用于执行减法函数以根据模拟输入信号和反馈信号产生减去的信号。 量化器耦合到减法单元，用于执行量化，以根据减法信号产生量化信号。 反馈单元耦合在减法单元和量化器之间，用于根据量化信号向减法单元提供反馈信号。 减法单元布置成减小量化器的信号输入摆幅。

公开(公告)号：US20090027246A1

公开(公告)日：2009-01-29

申请号：US12132202

申请日：2008-06-03

申请人： Kang-Wei Hsueh ,  Yu-Hsuan Tu

发明人： Kang-Wei Hsueh ,  Yu-Hsuan Tu

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1019 ,  H03M1/162 ,  H03M1/164

摘要： The invention provides an analog-to-digital converter (ADC). The ADC comprises a plurality of stages connected in series, a gain error correction module, and a look-ahead module. Each of the stages derives a stage output value from a stage input signal and generates a stage output signal as the stage input signal of a subsequent stage, wherein one of the stages is selected as a target stage for estimating a gain value thereof. The gain error correction module delivers a correction number to the target stage to affect the stage output signal of the target stage and the stage output values of subsequent stages of the target stage, receives at least one auxiliary output value from a look-ahead module dedicated to the target stage, and derives an error estimate of the gain value of the target stage from the stage output values and the auxiliary output value. The look-ahead module generates the auxiliary output value according to the stage output value of the target stage, wherein the auxiliary output value is not affected by the correction number.

摘要翻译： 本发明提供了一种模拟 - 数字转换器（ADC）。 ADC包括串联连接的多个级，增益误差校正模块和预先模块。 每个级从级输入信号导出级输出值，并产生级输出信号作为后级级的级输入信号，其中级中的一级被选作用于估计其增益值的目标级。 增益误差校正模块向目标级提供校正数，以影响目标级的级输出信号和目标级的后续级的级输出值，从预先的模块专用接收至少一个辅助输出值 到目标阶段，并且从舞台输出值和辅助输出值导出目标舞台的增益值的误差估计。 先行模块根据目标级的级输出值生成辅助输出值，其中辅助输出值不受校正数量的影响。

公开(公告)号：US07554469B2

公开(公告)日：2009-06-30

申请号：US12123522

申请日：2008-05-20

申请人： Yu-Hsuan Tu ,  Yi-Fu Chen ,  Kang-Wei Hsueh

发明人： Yu-Hsuan Tu ,  Yi-Fu Chen ,  Kang-Wei Hsueh

IPC分类号： H03M1/06

CPC分类号： H03M1/1033 ,  H03M1/164

摘要： The invention provides a method for gain error estimation in an analog-to-digital converter. In one embodiment, the analog-to-digital converter comprises a plurality of stages. A series of correction numbers applied to a target stage selected from the stages are correlated with a series of calculation values calculated according to digital output values of the stages to generate a series of gain error estimates. The series of gain error estimates are multiplied by a series of updating parameters to obtain a series of first values. A series of previous gain error values are multiplied by one minus the corresponding updating parameters to obtain a series of second values, wherein the series of previous gain values are obtained by delaying the present gain error values. The series of first values and the series of second values are correspondingly added to obtain a series of present gain error values for gain error correction.

摘要翻译： 本发明提供了一种用于模数转换器中增益误差估计的方法。 在一个实施例中，模数转换器包括多个级。 应用于从这些级选择的目标级的一系列校正数字与根据级的数字输出值计算的一系列计算值相关联，以产生一系列增益误差估计。 一系列增益误差估计乘以一系列更新参数，以获得一系列第一个值。 一系列先前的增益误差值乘以1减去对应的更新参数以获得一系列第二值，其中通过延迟当前的增益误差值来获得先前增益值的一系列。 相应地增加一系列第一值和一系列第二值以获得一系列用于增益误差校正的当前增益误差值。

公开(公告)号：US07592938B2

公开(公告)日：2009-09-22

申请号：US12132202

申请日：2008-06-03

申请人： Kang-Wei Hsueh ,  Yu-Hsuan Tu

发明人： Kang-Wei Hsueh ,  Yu-Hsuan Tu

IPC分类号： H03M1/06

CPC分类号： H03M1/1019 ,  H03M1/162 ,  H03M1/164

摘要： The invention provides an analog-to-digital converter (ADC). The ADC comprises a plurality of stages connected in series, a gain error correction module, and a look-ahead module. Each of the stages derives a stage output value from a stage input signal and generates a stage output signal as the stage input signal of a subsequent stage, wherein one of the stages is selected as a target stage for estimating a gain value thereof. The gain error correction module delivers a correction number to the target stage to affect the stage output signal of the target stage and the stage output values of subsequent stages of the target stage, receives at least one auxiliary output value from a look-ahead module dedicated to the target stage, and derives an error estimate of the gain value of the target stage from the stage output values and the auxiliary output value. The look-ahead module generates the auxiliary output value according to the stage output value of the target stage, wherein the auxiliary output value is not affected by the correction number.

摘要翻译： 本发明提供了一种模拟 - 数字转换器（ADC）。 ADC包括串联连接的多个级，增益误差校正模块和预先模块。 每个级从级输入信号导出级输出值，并产生级输出信号作为后级级的级输入信号，其中级中的一级被选作用于估计其增益值的目标级。 增益误差校正模块向目标级提供校正数，以影响目标级的级输出信号和目标级的后续级的级输出值，从预先的模块专用接收至少一个辅助输出值 到目标阶段，并且从舞台输出值和辅助输出值导出目标舞台的增益值的误差估计。 先行模块根据目标级的级输出值生成辅助输出值，其中辅助输出值不受校正数量的影响。

公开(公告)号：US07816978B1

公开(公告)日：2010-10-19

申请号：US12505535

申请日：2009-07-20

申请人： Tien-Yu Lo ,  Chuan-Cheng Hsiao ,  Kang-Wei Hsueh

发明人： Tien-Yu Lo ,  Chuan-Cheng Hsiao ,  Kang-Wei Hsueh

IPC分类号： H03K5/00

CPC分类号： H03H1/02 ,  H03H7/0153 ,  H03H2210/043

摘要： An operating circuit includes an amplifier having a first input terminal coupled to a reference voltage; a first transconducting element for selectively generating a first current; a second transconducting element for selectively generating a second current; a resistive element having a first terminal coupled to the first transconducting element; a capacitive element having a first terminal selectively coupled to the second transconducting element; and a switching device. The switching device has a first configuration to connect the first terminal of the capacitive element to the second transconducting element and connect the first terminal of the resistive element to a second input terminal of the amplifier, and has a second configuration to disconnect the first terminal of the capacitive element from the second transconducting element and connect the second input terminal of the amplifier to the first terminal of the capacitive element instead of the first terminal of the resistive element.

摘要翻译： 操作电路包括具有耦合到参考电压的第一输入端的放大器; 用于选择性地产生第一电流的第一跨导元件; 用于选择性地产生第二电流的第二跨导元件; 电阻元件，其具有耦合到所述第一跨导元件的第一端子; 电容元件，其具有选择性地耦合到所述第二跨导元件的第一端子; 和开关装置。 开关装置具有将电容元件的第一端子连接到第二跨导元件并将电阻元件的第一端子连接到放大器的第二输入端子的第一配置，并且具有第二配置以将第一端子 来自第二跨导元件的电容元件，并且将放大器的第二输入端子连接到电容元件的第一端子，而不是电阻元件的第一端子。

公开(公告)号：US20090294944A1

公开(公告)日：2009-12-03

申请号：US12396450

申请日：2009-03-02

申请人： Yin-Chao Huang ,  Shi-Bai Chen ,  Kang-Wei Hsueh ,  Hung-Sung Li

发明人： Yin-Chao Huang ,  Shi-Bai Chen ,  Kang-Wei Hsueh ,  Hung-Sung Li

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/49575 ,  H01L23/49531 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48145 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.

摘要翻译： 半导体器件组件包括第一半导体管芯，第二半导体管芯，至少一个半导体封装部件或另一个半导体管芯，第一导电元件和第二导电元件。 第一半导体管芯包括至少一个焊盘。 第二半导体管芯包括焊盘模块。 第一导电元件耦合在第二半导体管芯的焊盘模块和第一半导体管芯的焊盘之间，并且第二导电元件耦合在第二半导体管芯的焊盘模块和半导体封装部件之间或者 另一个半导体管芯，其中第一半导体管芯经由焊盘和焊盘模块以及第一和第二导电元件耦合到半导体封装部件或另一半导体管芯。