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    Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same
    2.
    发明申请
    Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same 有权
    超高压N型金属氧化物半导体（UHV NMOS）器件及其制造方法

    公开(公告)号：US20120241861A1

    公开(公告)日：2012-09-27

    申请号：US13070819

    申请日：2011-03-24

    申请人： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    发明人： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.

    摘要翻译： 提供了具有改进性能的超高电压n型金属氧化物半导体（UHV NMOS）器件及其制造方法。 UHV NMOS包括P型材料的衬底; 设置在所述基板的一部分中的第一高压N阱（HVNW）区域; 与第一HVNW区域的一侧相邻的源极和体积p阱（PW），源极和体积PW包括源极和体积; 从源极和体积PW延伸到第一HVNW区域的一部分的栅极，以及设置在与栅极相对的第一HVNW区域的另一部分内的漏极; 设置在第一HVNW区域内的P顶层，位于漏极与源极和体PW之间的P顶层; 以及形成在P顶层上的n型注入层。

    LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE
    3.
    发明申请
    LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE 有权
    低耐电流性双向扩散MOS器件

    公开(公告)号：US20110204441A1

    公开(公告)日：2011-08-25

    申请号：US13100449

    申请日：2011-05-04

    申请人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

    发明人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

    摘要翻译： 提供了横向双扩散MOS器件。 该装置包括：具有第一导电类型的第一阱和具有布置在衬底中并且彼此相邻的第二导电类型的第二阱; 漏极和分别设置在第一和第二阱中的具有第一导电类型的源极区域; 设置在源极和漏极区域之间的第一阱上的场氧化物层（FOX）; 设置在延伸到FOX的源极和漏极区域之间的第二阱上的栅极导电层; 在所述基板和所述栅极导电层之间的栅极介电层; 在栅极导电层的一部分下方的第一阱中具有第一导电类型的掺杂区域和连接到漏极区域的FOX。 在掺杂区域和源极区域之间的第二阱中限定沟道区域。

    Single gate nonvolatile memory cell with transistor and capacitor
    4.
    发明授权
    Single gate nonvolatile memory cell with transistor and capacitor 有权
    具有晶体管和电容器的单门非易失性存储单元

    公开(公告)号：US07999296B2

    公开(公告)日：2011-08-16

    申请号：US12102637

    申请日：2008-04-14

    申请人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

    发明人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

    IPC分类号： H01L27/105 ,  H01L21/8239

    CPC分类号： H01L29/6659 ,  H01L27/11558 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/788

    摘要： A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.

    摘要翻译： 非易失性存储器集成电路在半导体衬底上具有半导体衬底和非易失性存储器件。 该器件在半导体衬底上具有晶体管和电容器，以及连接晶体管的栅极区域和电容器的共用浮置栅极。 晶体管至少具有限定源极和漏极区域的掺杂区域以及与源极和漏极区域重叠的三个其它掺杂区域。 还公开了具有多个这种非易失性存储器件的非易失性存储器电路以及用于使非易失性存储器电路具有一个或多个这种非易失性存储器件的方法

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体结构及其制造方法

    公开(公告)号：US20130265102A1

    公开(公告)日：2013-10-10

    申请号：US13442340

    申请日：2012-04-09

    申请人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Ching-Lin Chan ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    发明人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Ching-Lin Chan ,  Shih-Chin Lien ,  Shyi-Yuan Wu

    IPC分类号： H01L29/808 ,  G11C5/14 ,  H01L21/337

    CPC分类号： H01L29/66901 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/808

    摘要： A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type formed in the deep well and extending down from the surface of the substrate; and a second well having the second conductive type formed in the deep well and extending down from the surface of the substrate, and the second well adjacent to the first well. The first well includes a block region and plural finger regions joined to one side of the block region, while the second well includes plural channel regions interlaced with the finger regions to separate the finger regions.

    摘要翻译： 提供了半导体结构及其制造方法。 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 第一阱具有形成在深阱中并从衬底表面向下延伸的第一导电类型; 以及第二阱，其具有形成在深阱中并从衬底的表面向下延伸的第二导电类型，以及与第一阱相邻的第二阱。 第一阱包括连接到块区域的一侧的块区域和多个指状区域，而第二阱包括与手指区域交织的多个沟道区域以分离手指区域。

    Low on-resistance lateral double-diffused MOS device
    10.
    发明授权
    Low on-resistance lateral double-diffused MOS device 有权
    低导通电阻横向双扩散MOS器件

    公开(公告)号：US08362558B2

    公开(公告)日：2013-01-29

    申请号：US13100449

    申请日：2011-05-04

    申请人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

    发明人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

    IPC分类号： H01L29/02

    CPC分类号： H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

    摘要翻译： 提供了横向双扩散MOS器件。 该装置包括：具有第一导电类型的第一阱和具有布置在衬底中并且彼此相邻的第二导电类型的第二阱; 漏极和分别设置在第一和第二阱中的具有第一导电类型的源极区域; 设置在源极和漏极区域之间的第一阱上的场氧化物层（FOX）; 设置在延伸到FOX的源极和漏极区域之间的第二阱上的栅极导电层; 在所述基板和所述栅极导电层之间的栅极介电层; 在栅极导电层的一部分下方的第一阱中具有第一导电类型的掺杂区域和连接到漏极区域的FOX。 在掺杂区域和源极区域之间的第二阱中限定沟道区域。