摘要:
A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor.
摘要:
A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.
摘要:
A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type formed in the deep well and extending down from the surface of the substrate; and a second well having the second conductive type formed in the deep well and extending down from the surface of the substrate, and the second well adjacent to the first well. The first well includes a block region and plural finger regions joined to one side of the block region, while the second well includes plural channel regions interlaced with the finger regions to separate the finger regions.
摘要:
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
摘要:
A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type.
摘要:
A semiconductor device comprises a semiconductor substrate, a lateral semiconductor diode, a field insulation structure, and a polysilicon resistor. The diode is formed in a surface region of the semiconductor substrate, and includes a cathode electrode and an anode electrode. The field insulation structure is disposed between the cathode and anode electrodes. The polysilicon resistor is formed over the field insulation structure, and between the cathode and anode electrodes. The polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated from the anode electrode.
摘要:
A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.
摘要:
An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.
摘要:
A portable toilet comprising a toilet bowl and a paper-made surrounding shield. The surrounding shield is made from a rectangular paper board which has three folding lines dividing the paper board into four equal quarters serving as two lateral walls, a door board and a rear wall of the surrounding shield. An upper half of each folding line is cut open to form a fissure. The paper board further has a transverse middle folding line at which an upper half of each quarter can be folded outward. A male and female fastening belt set is disposed at each fissure to support the four walls upright. A male and female fastening belt set is disposed at the door board of the surrounding shield for closing the door board. The toilet bowl is made by means of cutting a hard thick paper board into a square body with four close faces. Reinforcing ribs are disposed on outer faces of the four walls for strengthening the toilet bowl. Two hook members are disposed on inner faces of the toilet bowl for hooking a plastic bag to contain excretion. A seat pad board integrally extends from upper edge of each of two opposite walls and is cut with arch notch to suit the hip portion of a user. The seat pad board is foldable toward the other to be supported on the upper edges of the other two opposite walls for the user to sit thereon.
摘要:
An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.