公开(公告)号：US09465241B2

公开(公告)日：2016-10-11

申请号：US13703077

申请日：2012-09-26

申请人： JinJie Wang ,  Cheng-Hung Chen

发明人： JinJie Wang ,  Cheng-Hung Chen

IPC分类号： G01R31/26 ,  G02F1/13 ,  G02F1/1337

CPC分类号： G02F1/1303 ,  G02F1/133711 ,  G02F2001/133715

摘要： The present invention discloses an apparatus for applying curing voltages to a liquid crystal substrate. The apparatus includes a plurality of probes, a detecting unit, and an alarm unit. The probes are utilized to apply a voltage to the liquid crystal substrate. The detecting unit is electrically coupled to the probes for determining whether the curing voltages are within a threshold range. The alarm unit is electrically coupled to the detecting unit for giving an alarm prompt when the voltage is not within the threshold range, so as to remind a person without delay. Therefore, the curing voltage applying apparatus of the present invention is capable of increasing product yield, so as to reduce production costs.

摘要翻译： 本发明公开了一种向液晶基板施加固化电压的装置。 该装置包括多个探针，检测单元和报警单元。 利用探针对液晶基板施加电压。 检测单元电耦合到探针，以确定固化电压是否在阈值范围内。 警报单元电耦合到检测单元，用于当电压不在阈值范围内时提供报警提示，以便不延迟地提醒人。 因此，本发明的固化电压施加装置能够提高产品成品率，从而降低生产成本。

公开(公告)号：US09007556B2

公开(公告)日：2015-04-14

申请号：US13521708

申请日：2012-06-01

申请人： Cheng-hung Chen

发明人： Cheng-hung Chen

IPC分类号： G02F1/1339 ,  G02F1/1345 ,  G02F1/136 ,  G09G5/02 ,  G02F1/1333 ,  G02F1/137

CPC分类号： G02F1/136 ,  G02F1/1309 ,  G02F1/1333 ,  G02F1/133351 ,  G02F1/1345 ,  G02F2001/13775 ,  G09G5/02

摘要： The present invention provides a substrate for array process of panel display device, which includes a cell switch and a PVSA mode pad set. Cell switch includes a plurality of switches, with each connected to a pad in shorting bar pad set. PSVA mode pad set includes a scan pad and a data pad. Scan pad is connected through some switches of cell switch to scan lines, and data pad is connected through some switches of cell switch to data lines. In this manner, the present invention reduces the number of pads in PSVA mode pad set to simplify peripheral routes.

摘要翻译： 本发明提供一种面板显示装置的阵列处理用基板，其包括单元开关和PVSA模式垫组。 单元开关包括多个开关，每个开关连接到短路棒组中的垫。 PSVA模式焊盘组包括扫描焊盘和数据焊盘。 扫描板通过单元开关的一些开关连接到扫描线，数据焊盘通过单元开关的一些开关连接到数据线。 以这种方式，本发明减少了PSVA模式焊盘组中的焊盘的数量，以简化外围路由。

公开(公告)号：US08879013B2

公开(公告)日：2014-11-04

申请号：US13503374

申请日：2012-01-16

申请人： Cheng-Hung Chen

发明人： Cheng-Hung Chen

IPC分类号： G02F1/136

CPC分类号： H01L29/41733 ,  G09G3/3648 ,  G09G2300/0465 ,  H01L27/124

摘要： A thin-film transistor liquid crystal display device includes: a substrate and a signal line, a scan line, a pixel electrode, and a thin-film transistor that are formed on the substrate. The signal line and the scan line are arranged to intersect each other. The pixel electrode is located in a pixel display zone enclosed by the intersected signal line and scan line. The thin-film transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is electrically connected to the scan line. The drain terminal is electrically connected to the signal line. The source terminal is arranged at a position corresponding to the intersection of the signal line and the scan line and is electrically connected to the pixel electrode.

摘要翻译： 薄膜晶体管液晶显示装置包括：基板和形成在基板上的信号线，扫描线，像素电极和薄膜晶体管。 信号线和扫描线被布置成彼此相交。 像素电极位于由交叉的信号线和扫描线包围的像素显示区域中。 薄膜晶体管包括栅极端子，源极端子和漏极端子。 栅极端子与扫描线电连接。 漏极端子与信号线电连接。 源极端子配置在与信号线和扫描线的交叉点对应的位置，与电极连接。

公开(公告)号：US08830438B2

公开(公告)日：2014-09-09

申请号：US13576401

申请日：2012-06-21

申请人： Cheng-hung Chen ,  Zui Wang

发明人： Cheng-hung Chen ,  Zui Wang

IPC分类号： G02F1/1339 ,  G02F1/13 ,  G02F1/1335 ,  H01L27/15

CPC分类号： G02F1/1335 ,  G02F1/13 ,  G02F1/133351 ,  G02F1/1339 ,  G02F2001/133388 ,  G02F2202/28 ,  H01L27/156

摘要： The present invention relates to a liquid crystal display (LCD) panel and its manufacturing method. The LCD panel comprises a first substrate, a second substrate, a sealant, and a barrier wall. The first substrate and the second substrate are disposed relatively. The sealant disposed surrounding between the first substrate and the second substrate. The barrier wall is disposed at the outer side of the area surrounded by the sealant, and the barrier wall is respectively abutted against the first substrate and the second substrate. In summary, the present invention could improve the overflow of the sealant, reducing the difficulty for narrow frame design and the requirement for cutting precision of the LCD panel.

摘要翻译： 本发明涉及液晶显示（LCD）面板及其制造方法。 LCD面板包括第一基板，第二基板，密封剂和阻挡壁。 第一基板和第二基板相对设置。 密封剂设置在第一基板和第二基板之间。 阻挡壁设置在由密封剂包围的区域的外侧，并且阻挡壁分别抵靠第一基板和第二基板。 总之，本发明可以改善密封剂的溢出，减少了窄框架设计的难度和对LCD面板的切割精度的要求。

公开(公告)号：US20140034952A1

公开(公告)日：2014-02-06

申请号：US13582746

申请日：2012-08-03

申请人： Cheng-hung Chen

发明人： Cheng-hung Chen

IPC分类号： H01L29/786 ,  H01L33/08

CPC分类号： H01L27/1288 ,  H01L27/0251 ,  H01L27/124 ,  H01L29/41733

摘要： The present invention provides a manufacturing method for array substrate, including: forming a first conductive layer, a first isolator layer, a second conductive layer and a second isolator layer on a substrate from bottom up, the first conductive layer for forming electrically connected scan line and control terminal of switch transistor, performing dry etch on the second isolator layer to form via hole, and forming a third conductive layer on the second isolator layer for forming data line. The present invention also provides an arrays substrate and a liquid crystal display device. As such, the present invention can reduce the possibility of electrostatic explosion during array substrate manufacturing process and improve the yield rate of array substrate.

摘要翻译： 本发明提供一种阵列基板的制造方法，其特征在于，包括：从下向上在基板上形成第一导电层，第一隔离层，第二导电层和第二隔离层，形成电连接的扫描线的第一导电层 和开关晶体管的控制端子，在第二隔离层上进行干蚀刻以形成通孔，并在第二隔离层上形成第三导电层以形成数据线。 本发明还提供一种阵列基板和液晶显示装置。 因此，本发明可以降低阵列基板制造工序中的静电爆炸的可能性，提高阵列基板的成品率。

公开(公告)号：US20130320243A1

公开(公告)日：2013-12-05

申请号：US13484524

申请日：2012-05-31

申请人： Cheng-Hung Chen ,  Shih-Chi Wang ,  Jeng-Horng Chen ,  Burn Jeng Lin

发明人： Cheng-Hung Chen ,  Shih-Chi Wang ,  Jeng-Horng Chen ,  Burn Jeng Lin

IPC分类号： G21K5/10

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  H01J2237/31761

摘要： The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.

摘要翻译： 本公开提供了一种通过电子束光刻系统增加晶片通过量的方法。 该方法包括使用电子束写入器的最大扫描狭缝宽度（MSSW）扫描晶片。 通过限制集成电路（IC）场尺寸以允许MSSW覆盖整个场，MSSW被应用于减小晶片的扫描通道，从而增加吞吐量。 当用MSSW扫描晶片时，下一个扫描通道数据可以重新排列并加载到存储器缓冲器中。 因此，一旦一个扫描通道完成，读取存储器缓冲器中的下一个扫描通道数据进行扫描。

公开(公告)号：US08563224B1

公开(公告)日：2013-10-22

申请号：US13487850

申请日：2012-06-04

申请人： Cheng-Hung Chen ,  Pei-Shiang Chen ,  Shih-Chi Wang ,  Jeng-Horng Chen

发明人： Cheng-Hung Chen ,  Pei-Shiang Chen ,  Shih-Chi Wang ,  Jeng-Horng Chen

IPC分类号： G03C5/00 ,  G03F1/20

CPC分类号： G06F17/50 ,  G03C5/00 ,  G03F1/20 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01J2237/31769 ,  Y10S430/143

摘要： The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

摘要翻译： 本公开提供了通过电子束光刻系统增加晶片生产量的抖动方法。 抖动方法从顶点图生成边缘图。 顶点图是从集成电路设计布局（如原始图案位图）生成的。 也从集成电路设计布局生成灰色地图（也称为图案灰度图）。 通过将边缘图与灰度图组合，生成修改后的集成电路设计布局（修改图案位图），供电子束光刻系统使用。

公开(公告)号：US20130215366A1

公开(公告)日：2013-08-22

申请号：US13510932

申请日：2012-02-23

申请人： Cheng-hung Chen

发明人： Cheng-hung Chen

IPC分类号： G02F1/1335 ,  B05D5/06 ,  B05D5/12

CPC分类号： G02F1/1339 ,  G02F1/13378 ,  G02F2001/133388

摘要： This invention discloses a liquid crystal display and a method making the same. The liquid crystal display panel includes an array substrate, a color filter substrate, a liquid crystal layer, a first and second transfer pads. The first transfer pad is disposed on the array substrate, and the second transfer pad is disposed onto the color filter substrate, and is electrically interconnected with the first transfer pad. Wherein the first and second transfer pads are surface treated to reduce the surface tension thereof before deployment of alignment layers. By this arrangement, the non-active border along the peripheral of the liquid crystal display can be reduced, and a liquid crystal display with narrowed border is achieved.

摘要翻译： 本发明公开了一种液晶显示器及其制造方法。 液晶显示面板包括阵列基板，滤色器基板，液晶层，第一和第二转印垫。 第一传送焊盘设置在阵列基板上，第二传输焊盘设置在滤色器基板上，并与第一传送焊盘电互连。 其中第一和第二转移垫被表面处理以在展开定向层之前降低其表面张力。 通过这种布置，可以减小沿着液晶显示器周边的非活动边界，并实现具有窄边框的液晶显示器。

公开(公告)号：US20130215348A1

公开(公告)日：2013-08-22

申请号：US13503656

申请日：2012-02-23

申请人： Cheng-Hung Chen

发明人： Cheng-Hung Chen

IPC分类号： H01L33/08 ,  G02F1/136

CPC分类号： G02F1/1362 ,  G02F2001/134345 ,  G02F2201/123

摘要： The present invention discloses a thin-film transistor (TFT) liquid crystal display device, a substrate, and a manufacturing method thereof. The TFT substrate includes: a glass substrate and signal lines, scan lines, a first pixel electrode, a second pixel electrode, a common electrode, and the TFT. The first pixel electrode and the second pixel electrode at least partially overlap each other. The second pixel electrode forms a plurality of horizontally arranged slits and the first pixel electrode forms a hollow structure in a portion overlapping the second pixel electrode. Through the above method, the present invention increases transmittance, improve view angle color shift, and improve the quality of image.

摘要翻译： 本发明公开了一种薄膜晶体管（TFT）液晶显示装置，基板及其制造方法。 TFT基板包括：玻璃基板和信号线，扫描线，第一像素电极，第二像素电极，公共电极和TFT。 第一像素电极和第二像素电极至少部分地彼此重叠。 第二像素电极形成多个水平布置的狭缝，并且第一像素电极在与第二像素电极重叠的部分中形成中空结构。 通过上述方法，本发明提高透光率，提高视角色偏，提高图像质量。

公开(公告)号：US20130154679A1

公开(公告)日：2013-06-20

申请号：US13381071

申请日：2011-12-16

申请人： Cheng-hung Chen

发明人： Cheng-hung Chen

IPC分类号： G01R31/26

CPC分类号： G09G3/006

摘要： Disclosed is a testing system, which includes a thin film transistor substrate. The thin film transistor substrate includes a plurality of thin film transistors and a plurality of connecting pads. Each of the thin film transistors includes a first electrode, a second electrode, and a third electrode. The thin film transistor substrate further includes a testing pad. One of the first electrode and the second electrode of each of the thin film transistors is electrically connected with one of the connecting pads. The third electrode and the other one of the first electrode and the second electrode of each of the thin film transistors are electrically connected with the testing pad. The testing system of the present invention is capable of decreasing the cost of the testing system and the complexity of disposed circuits.

摘要翻译： 公开了一种包括薄膜晶体管基板的测试系统。 薄膜晶体管基板包括多个薄膜晶体管和多个连接焊盘。 每个薄膜晶体管都包括第一电极，第二电极和第三电极。 薄膜晶体管基板还包括测试垫。 每个薄膜晶体管的第一电极和第二电极之一与连接焊盘中的一个电连接。 每个薄膜晶体管的第三电极和第一电极和第二电极中的另一个与测试焊盘电连接。 本发明的测试系统能够降低测试系统的成本和设置电路的复杂性。