公开(公告)号：US07444615B2

公开(公告)日：2008-10-28

申请号：US11139551

申请日：2005-05-31

申请人： Gokhan Percin ,  Ram S. Ramanujam ,  Franz X. Zach ,  Abdurrahman Sezginer ,  Chi-Song Horng ,  Roy Prasad

发明人： Gokhan Percin ,  Ram S. Ramanujam ,  Franz X. Zach ,  Abdurrahman Sezginer ,  Chi-Song Horng ,  Roy Prasad

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F1/44 ,  G03F1/68

摘要： A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.

摘要翻译： 提供了一种产生OPC模型的方法，其考虑了在制造半导体芯片的过程中发生的跨晶片变化。 更具体地，提供了一种用于生成OPC模型的方法，其考虑了在基于在“晶片甜点”处测量的测试图案的参数的制造半导体芯片的过程期间发生的跨晶片变化，以便到达 准确模型。

公开(公告)号：US20060117778A1

公开(公告)日：2006-06-08

申请号：US11249321

申请日：2005-10-14

申请人： Sai Oh ,  Bong Park ,  Chi Song ,  Ju Kim ,  Se Chang ,  Baik Chung

发明人： Sai Oh ,  Bong Park ,  Chi Song ,  Ju Kim ,  Se Chang ,  Baik Chung

IPC分类号： F25B13/00 ,  F25B27/00

CPC分类号： F25B27/00 ,  F25B29/003 ,  F25B2339/047 ,  F25B2400/04

摘要： A cooling/heating system is disclosed which includes a compressor, an indoor heat exchanger, an expansion device, and an outdoor heat exchanger which are connected in series via a refrigerant line, wherein a refrigerant, which flows through the refrigerant line, heat-exchanges with supply water. A method for controlling the cooling/heating system is also disclosed.

摘要翻译： 公开了一种冷却/加热系统，其包括通过制冷剂管线串联连接的压缩机，室内热交换器，膨胀装置和室外热交换器，其中流过制冷剂管线的制冷剂进行热交换 供水。 还公开了一种用于控制冷却/加热系统的方法。

公开(公告)号：US06738788B1

公开(公告)日：2004-05-18

申请号：US10124860

申请日：2002-04-17

申请人： Chi-Song Horng ,  Keith Lofstrom

发明人： Chi-Song Horng ,  Keith Lofstrom

IPC分类号： G06F1730

CPC分类号： G06F17/30286 ,  Y10S707/99942 ,  Y10S707/99945

摘要： A database system accesses database records referenced by a binary number key having two fields, a typeID field containing only deterministic bits, and a uniqueID field permissibly containing one or more non-deterministic bits at any bit positions therein. The database system maintains a set of databases, each being identified by a separate value of the typeID field of the binary number key. The records of each database are allocated among a plurality of bins, with each bin being identified (keyed) by separate value of a binID field, and with each record being identified (keyed) by a separate value of a recID field. The database system locates a record of interest referenced by the binary number key by first selecting a particular one of the databases that is identified by the typeID field of the binary number key. It then compares a portion of selected bits of the binary number key's uniqueID field to binID values identifying bins of the selected database to determine a subset of the bins that may include the record of interest. The database system then compares the full uniqueID field of the binary number key to the recIDs values for records of the subset of bins to determine which particular recID field identifies the record of interest.

摘要翻译： 数据库系统访问由具有两个字段的二进制数字键引用的数据库记录，仅包含确定性位的typeID字段以及在其中的任何位位置允许包含一个或多个非确定性位的唯一ID字段。 数据库系统维护一组数据库，每个数据库由二进制数字键的typeID字段的单独值标识。 每个数据库的记录被分配在多个箱之间，其中每个仓被binID字段的分开的值识别（加密），并且每个记录由recID字段的单独的值标识（加密）。 数据库系统通过首先选择由二进制数字键的typeID字段标识的特定数据库来定位由二进制数字键引用的感兴趣的记录。 然后，它将二进制数密钥的唯一ID字段的所选位的一部分与识别所选数据库的存储区的binID值进行比较，以确定可能包括感兴趣的记录的仓的子集。 数据库系统然后将二进制数字键的完整uniqueID字段与bin的子集的记录的recIDs值进行比较，以确定哪个特定的recID字段标识感兴趣的记录。

公开(公告)号：US5710550A

公开(公告)日：1998-01-20

申请号：US516322

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

IPC分类号： G06F15/173 ,  H04Q11/04 ,  H03K17/0412

CPC分类号： G06F15/17375 ,  H04Q11/0478

摘要： A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data. The FPID further includes a memory controller for receiving each command from the host controller and for writing data included in the command into each memory cell of a particular subset of the first and second memory cells upon receipt of the command. The address included in the command indicates the particular subset into which the controller is to write the data. The number of memory cells included in the particular subset is a variable function of the address.

摘要翻译： 现场可编程互连设备（FPID）响应于来自主机控制器的命令，有选择地在信号端口之间路由信号。 每个命令包括地址和数据。 FPID包括开关单元阵列，每个开关单元互连一个单独的端口对，并且每个具有第一和第二控制信号输入。 当第一和第二控制信号均被断言时，开关单元在其互连的一对端口之间提供信号路径。 FPID包括用于存储数据的第一和第二组存储器单元。 每个第一存储器单元对应于开关单元中的单独单元，并根据其存储的数据选择性地断言或解除输入到相应开关单元的第一控制信号。 每个第二存储器单元对应于单独的开关单元组，并根据其存储的数据选择性地断言或解除输入到相应组的每个开关单元的第二控制信号。 FPID还包括存储器控制器，用于从主机控制器接收每个命令，并且用于在接收到命令时将包括在命令中的数据写入第一和第二存储器单元的特定子集的每个存储单元。 命令中包含的地址表示控制器写入数据的特定子集。 包含在特定子集中的存储单元的数量是地址的可变函数。

公开(公告)号：US5530814A

公开(公告)日：1996-06-25

申请号：US333290

申请日：1994-11-02

申请人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

发明人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

IPC分类号： G06F13/36 ,  G06F15/173 ,  H03K19/173 ,  H03K19/177 ,  H05K1/00 ,  G06F13/00

CPC分类号： G06F15/17375 ,  H03K19/1736 ,  H03K19/17704 ,  H05K1/0286

摘要： A hierarchical crossbar switch includes several switch arrays, each switch array including several switch cells. Each switch cell interconnects a unique pair of signal ports and provides a bi-directional signal path between the signal ports it interconnects when switched on by an enabling signal. A first memory array stores input data indicating particular switch cells to be switched on. A second memory array stores input data indicating particular ones of the switch arrays to be enabled. The crossbar switch also includes a logic cell array that reads the data stored in the first and second memories and sends separate control signals to each switch cell. Each control signal switches on the switch cell to which it is sent when data in the first and second memory arrays indicate both that the switch cell is to be switched on and that the switch cell array including the switch cell is to be enabled.

摘要翻译： 分层交叉开关包括几个开关阵列，每个开关阵列包括几个开关单元。 每个开关单元互连一个唯一的一对信号端口，并且在通过使能信号接通时在互连的信号端口之间提供双向信号路径。 第一存储器阵列存储指示要接通的特定开关单元的输入数据。 第二存储器阵列存储指示要启用的特定开关阵列的输入数据。 交叉开关还包括逻辑单元阵列，其读取存储在第一和第二存储器中的数据，并向每个开关单元发送单独的控制信号。 当第一和第二存储器阵列中的数据指示要切换开关单元并且包括开关单元的开关单元阵列将被启用时，每个控制信号切换其所发送的开关单元。

公开(公告)号：US5428750A

公开(公告)日：1995-06-27

申请号：US171751

申请日：1993-12-21

申请人： Wen-Jai Hsieh ,  Chi-Song Horng

发明人： Wen-Jai Hsieh ,  Chi-Song Horng

IPC分类号： H03K19/173 ,  H05K1/00 ,  G06F13/00

CPC分类号： H03K19/1736 ,  H05K1/0286

摘要： A field programmable logic module provides a set of sockets for mounting electronic components, a set of connector pins for providing external access to the board, and a set of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports can be programmed to provide various types of buffering and logic operations on the signals routed by the FPIDs.

摘要翻译： 现场可编程逻辑模块提供一组插座，用于安装电子元件，一组连接器引脚，用于提供对板的外部访问，以及一组现场可编程互连设备（FPID）。 FPID是缓冲的，多端口交叉点开关，其可以由主机计算机来选择性地将安装在插座中的部件的端子彼此连接或连接到外部连接器引脚。 FPID端口中的信号缓冲器可以编程为对FPID路由的信号提供各种类型的缓冲和逻辑运算。

公开(公告)号：US5426738A

公开(公告)日：1995-06-20

申请号：US171752

申请日：1993-12-21

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

IPC分类号： H03K19/173 ,  H05K1/00 ,  G06F3/00

CPC分类号： H03K19/1736 ,  H05K1/0286

摘要： A field programmable circuit board provides a set of sockets for receiving electronic components, a set of connector pins for providing external access to the board and an array of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports automatically sense direction of flow of bidirectional signals routed by the FPIDs and buffer the signals in the appropriate direction. Each FPID buffer also samples and stores data indicating states of the buffered signals over several system clock cycles for subsequent read out by the host computer.

摘要翻译： 现场可编程电路板提供一组用于接收电子元件的插座，一组连接器引脚，用于提供对板的外部访问以及现场可编程互连器件（FPID）阵列。 FPID是缓冲的，多端口交叉点开关，其可以由主机计算机来选择性地将安装在插座中的部件的端子彼此连接或连接到外部连接器引脚。 FPID端口内的信号缓冲区会自动检测由FPID路由的双向信号的流向，并按适当的方向缓冲信号。 每个FPID缓冲器还在几个系统时钟周期上采样和存储指示缓冲信号状态的数据，以供主计算机随后读出。

公开(公告)号：US07318214B1

公开(公告)日：2008-01-08

申请号：US10841079

申请日：2004-05-07

申请人： Roy V. Prasad ,  Chi-Song Horng ,  Ram S. Ramanujam

发明人： Roy V. Prasad ,  Chi-Song Horng ,  Ram S. Ramanujam

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F1/76

摘要： The present invention provides a system and method of modifying the mask layout shapes of an integrated circuit layout design to compensate for reticle field location-specific systematic CD variations resulting from mask writing process variations, lens imperfections in lithographic patterning, and photoresist process variations. Called PLC (Process-optimized Layout Compensation), each set of compensation rules according to the present invention is specifically tailored for a particular mask-writer-patterning-tools-and-resist-process combination, and are performed on a reticle-wide basis. Furthermore, for each geometric shape in the mask layout, the amount of modification is determined based on a categorization of the type of the shape, the specific location in the reticle field the particular shape falls in, its context (i.e., surrounding patterns, orientation, etc.), as well as certain photoresist parameters to be used in the patterning process.

摘要翻译： 本发明提供了一种修改集成电路布局设计的掩模布局形状的系统和方法，以补偿由掩模写入过程变化，平版印刷图案中的晶体缺陷和光致抗蚀剂工艺变化导致的标线片位置特定系统CD变化。 被称为PLC（过程优化布局补偿），根据本发明的每组补偿规则是针对特定的掩模 - 写入器 - 图案形成 - 工具和 - 抗蚀剂 - 处理组合而专门设计的，并且在掩模版宽度的基础上执行 。 此外，对于掩模布局中的每个几何形状，修改量基于形状的类型的分类，特定形状所在的标线场中的特定位置，其上下文（即，周围图案，取向 等），以及在图案化工艺中使用的某些光刻胶参数。

公开(公告)号：US5465056A

公开(公告)日：1995-11-07

申请号：US333524

申请日：1994-11-02

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/0175

CPC分类号： H03K19/1736

摘要： A field programmable interconnect device (FPID) includes a set of ports and an array of switch cells for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray. Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a "rapid connect" mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports.

摘要翻译： 现场可编程互连设备（FPID）包括一组端口和用于选择性地互连端口对的开关单元阵列。 开关单元被组织成子阵列的层次结构，并且为每个子阵列提供控制单元。 每个开关单元包括交叉点开关和单位存储器。 存储在存储器中的位表示交换机是否在使能时互连其对FPID I / O端口。 存储在每个控制单元中的数据位指示相关子阵列的所有开关单元是否被使能。 在“快速连接”操作模式中，FPID响应于识别单元的并行输入数据并指示要存储在单元中的位的状态来设置存储在任何单独的开关或控制单元中的位的状态。 在快速连接模式下，FPID可以被编程为快速切换各个线路之间或连接到其端口的并行总线之间的连接。

公开(公告)号：US5428800A

公开(公告)日：1995-06-27

申请号：US960965

申请日：1992-10-13

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng ,  Keith Lofstrom

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng ,  Keith Lofstrom

IPC分类号： H03K19/173 ,  G06F13/40 ,  H03K19/0175 ,  H03K19/177 ,  G06F13/00 ,  H03K17/16

CPC分类号： G06F13/4004 ,  H03K19/017581 ,  H03K19/01759

摘要： A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.

摘要翻译： 双向缓冲器包括第一和第二单向缓冲器，连接用于在第一和第二总线之间以相反方向重新发送信号。 当外部总线驱动器将第一总线拉低时，第一单向缓冲器将第二总线拉低，并产生禁止第二单向缓冲器主动驱动第一总线的信号。 当外部总线驱动器允许第一总线返回到高逻辑电平时，第一单向缓冲器临时向第二总线提供高充电电流，以快速将其拉起。 类似地，当外部总线驱动器将第二总线拉低时，第二单向缓冲器将第一总线拉低，并产生禁止第一单向缓冲器主动驱动第二总线的信号。 当外部总线驱动器允许第二总线返回到高逻辑电平时，第二缓冲器暂时向第一总线提供高充电电流以快速将其拉起。 双向缓冲器包括用于存储和读出表示第一总线上的信号的连续逻辑状态的数据的寄存器，从而提供出现在总线上的数据历史。