公开(公告)号：US07616657B2

公开(公告)日：2009-11-10

申请号：US11402417

申请日：2006-04-11

申请人： Sergey Shumarayev ,  Bill W Bereza ,  Chong H Lee ,  Rakesh H Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W Bereza ,  Chong H Lee ,  Rakesh H Patel ,  Wilson Wong

IPC分类号： H04J3/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07590174B2

公开(公告)日：2009-09-15

申请号：US11312181

申请日：2005-12-20

申请人： Wilson Wong ,  Rakesh H Patel ,  Sergey Shumarayev ,  Tin H Lai

发明人： Wilson Wong ,  Rakesh H Patel ,  Sergey Shumarayev ,  Tin H Lai

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 以这种方式，在信号归一化块中执行低频内容的受控调整。

公开(公告)号：US07812659B1

公开(公告)日：2010-10-12

申请号：US11432420

申请日：2006-05-10

申请人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

发明人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

IPC分类号： G06F1/04 ,  H04L7/00

CPC分类号： H03L7/22 ,  G06F1/06

摘要： A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.

摘要翻译： 可编程逻辑器件（“PLD”）等具有多个数据发送器通道。 某些电路由通道共享。 共享电路包括用于产生主时钟信号的至少一个锁相环（“PLL”）电路和用于基于主信号产生至少一个全局辅助时钟信号的全局分频器电路。 主要和全局辅助信号被分配到信道。 每个通道包括本地分频器电路，用于基于主信号产生至少一个本地辅助时钟信号。 每个通道还包括选择电路，用于选择由信道的时钟利用电路使用的全局或局部辅助信号。 时钟利用电路可以包括用于将数据从并行转换为串行形式的串行化器电路。

公开(公告)号：US07538578B2

公开(公告)日：2009-05-26

申请号：US11177034

申请日：2005-07-08

申请人： Ramanand Venkata ,  Chong H Lee ,  Rakesh H Patel

发明人： Ramanand Venkata ,  Chong H Lee ,  Rakesh H Patel

IPC分类号： H03K19/177 ,  G06F13/42

CPC分类号： H03K19/17744

摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

摘要翻译： 用于可编程逻辑器件的串行接口可以根据各种通信协议进行操作，并且包括接收器部分和发射器部分。 接收器部分至少包括字或字节对准级，去偏移级，速率补偿或匹配级，填充协议解码器级（例如，8B / 10B解码器电路或64B / 66B解码器电路），字节解串器 阶段，字节重排阶段和相位补偿阶段。 发射机部分至少包括相位补偿级，字节解串器级和填充协议编码器级（例如，8B / 10B编码器电路或64B / 66B编码器电路）。 每个阶段可能有多次出现相关的电路。 选择电路，例如多路复用器，为所使用的协议选择适当的阶段和每个阶段内的电路。

公开(公告)号：US07151397B2

公开(公告)日：2006-12-19

申请号：US10873578

申请日：2004-06-22

申请人： Stjepan W Andrasic ,  Rakesh H Patel ,  Chong H Lee

发明人： Stjepan W Andrasic ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： H03H11/26 ,  H03B5/24

CPC分类号： H03K5/133 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/0995 ,  H03L7/10

摘要： A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

公开(公告)号：US07525340B2

公开(公告)日：2009-04-28

申请号：US11230002

申请日：2005-09-19

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Chong H Lee

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： G09F7/38 ,  H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17704 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on separate dies from the remainder of the programmable logic device mounted on a common substrate), and one or both of the programmable logic regions and the conventional I/O regions, have contacts for metallization traces or other interconnections to connect the peripheral specialized regions to the remainder of the programmable logic device. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnections. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry.

摘要翻译： 具有一个或多个可编程逻辑区域和一个或多个常规输入/输出区域的可编程逻辑器件（PLD）还具有包括专用电路的一个或多个外围区域。 外围专用区域不连接到可编程逻辑器件的其余部分（并且可以在与安装在公共衬底上的可编程逻辑器件的其余部分分开的管芯上）制造，以及一个或两个可编程逻辑区域 常规I / O区域具有用于金属化迹线或其它互连的触点，以将外围专用区域连接到可编程逻辑器件的其余部分。 通过提供或不提供互连，可以在具有或不具有专用电路能力的情况下出售相同的PLD。 外围专业区域可能包括高速I / O（基本，高达约3 Gbps，增强，高达10-12 Gbps）以及其他类型的专用电路。

公开(公告)号：US07183797B2

公开(公告)日：2007-02-27

申请号：US10977952

申请日：2004-10-29

申请人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

发明人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： H03K19/173

CPC分类号： G06F13/385

摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

摘要翻译： 在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。 高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。 接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

公开(公告)号：US07436210B2

公开(公告)日：2008-10-14

申请号：US11655797

申请日：2007-01-18

申请人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

发明人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： H03K19/173

CPC分类号： G06F13/385

摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

摘要翻译： 在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。 高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。 接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

公开(公告)号：US07109743B2

公开(公告)日：2006-09-19

申请号：US11148046

申请日：2005-06-07

申请人： Sergey Y Shumarayev ,  Thomas H White ,  Rakesh H Patel ,  Wilson Wong

发明人： Sergey Y Shumarayev ,  Thomas H White ,  Rakesh H Patel ,  Wilson Wong

IPC分类号： H03K17/16

CPC分类号： H03K19/17744 ,  H03K19/018585 ,  H03K19/1778 ,  H04L25/0272 ,  H04L25/0286

摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

摘要翻译： 提供了具有差分I / O电路的可编程逻辑器件集成电路。 差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。 用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。 用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。

公开(公告)号：US6107854A

公开(公告)日：2000-08-22

申请号：US62379

申请日：1998-04-17

申请人： Wilson Wong ,  John E. Turner ,  Thomas H. White ,  Rakesh H Patel

发明人： Wilson Wong ,  John E. Turner ,  Thomas H. White ,  Rakesh H Patel

IPC分类号： H03K5/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03H11/26

CPC分类号： H03K19/00384 ,  H03K19/01721 ,  H03K19/018585 ,  H03K2005/00078

摘要： A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.

摘要翻译： 速度路径电路包括参考电路和可调节的驱动部件，其可以被接通或关断以改变速度路径，以便满足电路的最小延迟规范。 在一个实施例中，使用一个或多个差分放大器来检测示例电路元件的强度并产生参考信号。 可选实施例包括用于断开参考电路以避免任何直流电流消耗的机构。 本发明可以用于广泛的集成电路中，并且还可以用在可编程逻辑器件（PLD）中。 参考电路可以通过使用可编程逻辑元件与电源断开连接。