公开(公告)号：US20110317493A1

公开(公告)日：2011-12-29

申请号：US12826280

申请日：2010-06-29

Applicant: Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C16/04

CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract translation: 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

公开(公告)号：US20080076219A1

公开(公告)日：2008-03-27

申请号：US11943888

申请日：2007-11-21

Applicant: Chu-Ching Wu ,  Cheng-Ming Yih

Inventor： Chu-Ching Wu ,  Cheng-Ming Yih

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract translation: 闪存单元包括具有主表面的硅衬底，位于主表面附近的硅衬底的一部分中的源极区域和位于主表面附近的硅衬底的一部分中的漏极区域。 漏极区域与源极区域间隔开。 所述存储单元包括形成在所述主表面上的第一介电层，设置在所述第一介电层上方的浮置栅极，设置在所述浮置栅极上方的栅极间电介质层，设置在所述栅极间电介质层上方的控制栅极， 电介质层和设置在第二电介质层上的低k电介质间隔层。 第一电介质层覆盖源极和漏极之间的主表面的一部分。 第二电介质层围绕第一电介质层，控制栅极，栅极间电介质层和浮置栅极的外部部分。

公开(公告)号：US07319611B2

公开(公告)日：2008-01-15

申请号：US11339092

申请日：2006-01-25

Applicant: Chu-Ching Wu ,  Cheng-Ming Yih

Inventor： Chu-Ching Wu ,  Cheng-Ming Yih

IPC: G11C11/4063 ,  G11C11/4097 ,  G11C16/04 ,  G11C5/06

CPC classification number: H01L27/115 ,  H01L27/105

Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract translation: 存储器阵列包括掩埋扩散区域，向掩埋扩散区域提供电力的第一源极线，向掩埋扩散区域提供电能的第二源极线，具有第一沟道宽度的第一位线晶体管和第二位线 晶体管具有第二通道宽度。 第一位线晶体管靠近第一源极线并且电耦合到第一存储器单元。 第一位线晶体管设置在第一和第二源极线之间。 第二位线晶体管靠近第一位线晶体管并且电耦合到第二存储器单元。 第二位线晶体管设置在第一和第二源极线之间，并且比第一位线晶体管更远离第一源极线。 第二通道宽度大于第一通道宽度。

公开(公告)号：US20070042544A1

公开(公告)日：2007-02-22

申请号：US11204537

申请日：2005-08-16

Applicant: Chu-Ching Wu ,  Cheng-Ming Yih

Inventor： Chu-Ching Wu ,  Cheng-Ming Yih

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract translation: 闪存单元包括具有主表面的硅衬底，位于主表面附近的硅衬底的一部分中的源极区域和位于主表面附近的硅衬底的一部分中的漏极区域。 漏极区域与源极区域间隔开。 所述存储单元包括形成在所述主表面上的第一介电层，设置在所述第一介电层上方的浮置栅极，设置在所述浮置栅极上方的栅极间电介质层，设置在所述栅极间电介质层上方的控制栅极， 电介质层和设置在第二电介质层上的低k电介质间隔层。 第一电介质层覆盖源极和漏极之间的主表面的一部分。 第二电介质层围绕第一电介质层，控制栅极，栅极间电介质层和浮置栅极的外部部分。

公开(公告)号：US08508993B2

公开(公告)日：2013-08-13

申请号：US13567817

申请日：2012-08-06

Applicant: Yi-Fan Chang ,  Su-chueh Lo ,  Cheng-Ming Yi ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen Long Chang ,  Chun Hsiung Hung

Inventor： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng-Ming Yi ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen Long Chang ,  Chun Hsiung Hung

IPC: G11C11/34

CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract translation: 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

公开(公告)号：US08259499B2

公开(公告)日：2012-09-04

申请号：US12826280

申请日：2010-06-29

Applicant: Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C11/34

CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract translation: 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

公开(公告)号：US07846794B2

公开(公告)日：2010-12-07

申请号：US11943888

申请日：2007-11-21

Applicant: Chu-Ching Wu ,  Cheng-Ming Yih

Inventor： Chu-Ching Wu ,  Cheng-Ming Yih

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract translation: 闪存单元包括具有主表面的硅衬底，位于主表面附近的硅衬底的一部分中的源极区域和靠近主表面的硅衬底的一部分中的漏极区域。 漏极区域与源极区域间隔开。 所述存储单元包括形成在所述主表面上的第一介电层，设置在所述第一介电层上方的浮置栅极，设置在所述浮置栅极上方的栅极间电介质层，设置在所述栅极间电介质层上方的控制栅极， 电介质层和设置在第二电介质层上的低k电介质间隔层。 第一电介质层覆盖源极和漏极之间的主表面的一部分。 第二电介质层围绕第一电介质层，控制栅极，栅极间电介质层和浮置栅极的外部部分。

公开(公告)号：US20080308857A1

公开(公告)日：2008-12-18

申请号：US11762677

申请日：2007-06-13

Applicant: Cheng-Ming Yih ,  Chu-Ching Wu ,  Huei-Huarng Chen

Inventor： Cheng-Ming Yih ,  Chu-Ching Wu ,  Huei-Huarng Chen

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/115 ,  G11C16/3404 ,  G11C16/3409 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.

Abstract translation: 非易失性存储器件通过控制栅极结构中的电介质层以及整个栅极结构的物理方面，例如厚度，宽度，面积等来在正常擦除周期期间实现自会聚。 还可以在正常擦除周期期间通过在擦除周期期间斜坡施加到控制栅极的擦除电压来辅助自会聚。

公开(公告)号：US20120300553A1

公开(公告)日：2012-11-29

申请号：US13567817

申请日：2012-08-06

Applicant: Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C16/04

CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Abstract translation: 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

公开(公告)号：US08097912B2

公开(公告)日：2012-01-17

申请号：US11762677

申请日：2007-06-13

Applicant: Cheng-Ming Yih ,  Chu-Ching Wu ,  Huei-Huarng Chen

Inventor： Cheng-Ming Yih ,  Chu-Ching Wu ,  Huei-Huarng Chen

IPC: H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/115 ,  G11C16/3404 ,  G11C16/3409 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.

Abstract translation: 非易失性存储器件通过控制栅极结构中的电介质层以及整个栅极结构的物理方面，例如厚度，宽度，面积等来在正常擦除周期期间实现自会聚。 还可以在正常擦除周期期间通过在擦除周期期间斜坡施加到控制栅极的擦除电压来辅助自会聚。