公开(公告)号：US08461029B2

公开(公告)日：2013-06-11

申请号：US13566616

申请日：2012-08-03

申请人： Fengyi Jiang ,  Li Wang ,  Chunlan Mo ,  Wenqing Fang

发明人： Fengyi Jiang ,  Li Wang ,  Chunlan Mo ,  Wenqing Fang

IPC分类号： H01L21/0254

CPC分类号： H01L21/0262 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/06

摘要： A method for fabricating quantum wells by using indium gallium nitride (InGaN) semiconductor material includes fabricating a potential well on a layered group III-V nitride structure at a first predetermined temperature in a reactor chamber by injecting into the reactor chamber an In precursor gas and a Ga precursor gas. The method further includes, subsequent to the fabrication of the potential well, terminating the Ga precursor gas, maintaining a flow of the In precursor gas, and increasing the temperature in the reactor chamber to a second predetermined temperature while adjusting the In precursor gas flow rate from a first to a second flow rate. In addition, the method includes annealing and stabilizing the potential well at the second predetermined temperature while maintaining the second flow rate. The method also includes fabricating a potential barrier above the potential well at the second predetermined temperature while resuming the Ga precursor gas.

摘要翻译： 通过使用氮化铟镓（InGaN）半导体材料制造量子阱的方法包括在反应器室中的第一预定温度下在层状III-V族氮化物结构上制造势阱，通过将反应器中的In前体气体和 一种Ga前体气体。 该方法还包括在制造势阱之后，终止Ga前体气体，保持In前体气体的流动，并将反应器室中的温度升高到第二预定温度，同时调节In前体气体流速 从第一流量到第二流量。 此外，该方法包括在维持第二流量的同时在第二预定温度下退火和稳定势阱。 该方法还包括在恢复Ga前体气体的同时在第二预定温度下制造位于势阱上方的势垒。

公开(公告)号：US20120295422A1

公开(公告)日：2012-11-22

申请号：US13566616

申请日：2012-08-03

申请人： Fengyi Jiang ,  Li Wang ,  Chunlan Mo ,  Wenqing Fang

发明人： Fengyi Jiang ,  Li Wang ,  Chunlan Mo ,  Wenqing Fang

IPC分类号： H01L21/20

CPC分类号： H01L21/0262 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/06

摘要： A method for fabricating quantum wells by using indium gallium nitride (InGaN) semiconductor material includes fabricating a potential well on a layered group III-V nitride structure at a first predetermined temperature in a reactor chamber by injecting into the reactor chamber an In precursor gas and a Ga precursor gas. The method further includes, subsequent to the fabrication of the potential well, terminating the Ga precursor gas, maintaining a flow of the In precursor gas, and increasing the temperature in the reactor chamber to a second predetermined temperature while adjusting the In precursor gas flow rate from a first to a second flow rate. In addition, the method includes annealing and stabilizing the potential well at the second predetermined temperature while maintaining the second flow rate. The method also includes fabricating a potential barrier above the potential well at the second predetermined temperature while resuming the Ga precursor gas.

摘要翻译： 通过使用氮化铟镓（InGaN）半导体材料制造量子阱的方法包括在反应器室中的第一预定温度下在层状III-V族氮化物结构上制造势阱，通过将反应器中的In前体气体和 一种Ga前体气体。 该方法还包括在制造势阱之后，终止Ga前体气体，保持In前体气体的流动，并将反应器室中的温度升高到第二预定温度，同时调节In前体气体流速 从第一流量到第二流量。 此外，该方法包括在维持第二流量的同时在第二预定温度下退火和稳定势阱。 该方法还包括在恢复Ga前体气体的同时在第二预定温度下制造位于势阱上方的势垒。

公开(公告)号：US20080315212A1

公开(公告)日：2008-12-25

申请号：US11841116

申请日：2007-08-20

申请人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

发明人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

IPC分类号： H01L33/00 ,  H01L31/12

CPC分类号： H01L33/007 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L33/325

摘要： One embodiment of the present invention provides a method for fabricating a group III-V p-type nitride structure. The method comprises growing a first layer of p-type group III-V material with a first acceptor density in a first growing environment. The method further comprises growing a second layer of p-type group III-V material, which is thicker than the first layer and which has a second acceptor density, on top of the first layer in a second growing environment. In addition, the method comprises growing a third layer of p-type group III-V material, which is thinner than the second layer and which has a third acceptor density, on top of the second layer in a third growing environment.

摘要翻译： 本发明的一个实施例提供一种制造III-V族p型氮化物结构的方法。 该方法包括在第一生长环境中生长具有第一受体密度的第一层p型III-V族材料。 该方法还包括在第二生长环境中在第一层的顶部上生长第二层p型III-V族材料，该第二层厚度比第一层厚，并具有第二受体密度。 此外，该方法包括在第三生长环境中，在第二层的顶部上生长比第二层薄且具有第三受体密度的第三层p型III-V族材料。

公开(公告)号：US08431936B2

公开(公告)日：2013-04-30

申请号：US11841116

申请日：2007-08-20

申请人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

发明人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

IPC分类号： H01L29/26 ,  H01L29/06

CPC分类号： H01L33/007 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L33/325

摘要： One embodiment of the present invention provides a method for fabricating a group III-V p-type nitride structure. The method comprises growing a first layer of p-type group III-V material with a first acceptor density in a first growing environment. The method further comprises growing a second layer of p-type group III-V material, which is thicker than the first layer and which has a second acceptor density, on top of the first layer in a second growing environment. In addition, the method comprises growing a third layer of p-type group III-V material, which is thinner than the second layer and which has a third acceptor density, on top of the second layer in a third growing environment.

摘要翻译： 本发明的一个实施例提供一种制造III-V族p型氮化物结构的方法。 该方法包括在第一生长环境中生长具有第一受体密度的第一层p型III-V族材料。 该方法还包括在第二生长环境中在第一层的顶部上生长第二层p型III-V族材料，该第二层厚度比第一层厚，并具有第二受体密度。 此外，该方法包括在第三生长环境中，在第二层的顶部上生长比第二层薄且具有第三受体密度的第三层p型III-V族材料。

公开(公告)号：US20100219394A1

公开(公告)日：2010-09-02

申请号：US12159835

申请日：2007-08-31

申请人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

发明人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

IPC分类号： H01L33/06 ,  H01L33/30

CPC分类号： H01L33/0095 ,  H01L33/32 ,  H01L33/40

摘要： One embodiment of the present invention provides a method for fabricating a group III-V nitride structure with an ohmic-contact layer. The method involves fabricating a group III-V nitride structure with a p-type layer. The method further involves depositing an ohmic-contact layer on the p-type layer without first annealing the p-type layer. The method also involves subsequently annealing the p-type layer and the ohmic-contact layer in an annealing chamber at a predetermined temperature for a predetermined period of time, thereby reducing the resistivity of the p-type layer and the ohmic contact in a single annealing process.

摘要翻译： 本发明的一个实施例提供了一种用欧姆接触层制造III-V族氮化物结构的方法。 该方法包括用p型层制造III-V族氮化物结构。 该方法还包括在p型层上沉积欧姆接触层，而不首先退火p型层。 该方法还包括随后在预定温度下在退火室中退火预定时间段内的p型层和欧姆接触层，从而降低单一退火中p型层的电阻率和欧姆接触 处理。

公开(公告)号：US08053757B2

公开(公告)日：2011-11-08

申请号：US12159850

申请日：2007-08-31

申请人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo ,  Yong Pu ,  Chuanbing Xiong

发明人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo ,  Yong Pu ,  Chuanbing Xiong

IPC分类号： H01L29/06

CPC分类号： H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L33/007

摘要： One embodiment of the present invention provides a gallium nitride (GaN)-based semiconductor light-emitting device (LED) which includes an n-type GaN-based semiconductor layer (n-type layer); an active layer; and a p-type GaN-based semiconductor layer (p-type layer). The n-type layer is epitaxially grown by using ammonia gas (NH3) as the nitrogen source prior to growing the active layer and the p-type layer. The flow rate ratio between group V and group III elements is gradually reduced from an initial value to a final value. The GaN-based LED exhibits a reverse breakdown voltage equal to or greater than 60 volts.

摘要翻译： 本发明的一个实施例提供了一种包含n型GaN基半导体层（n型层）的基于氮化镓（GaN）的半导体发光器件（LED）。 活性层 和p型GaN类半导体层（p型层）。 在生长活性层和p型层之前，通过使用氨气（NH 3）作为氮源，外延生长n型层。 V组和III组元件之间的流量比从初始值逐渐减小到最终值。 GaN基LED呈现等于或大于60伏的反向击穿电压。

公开(公告)号：US07888779B2

公开(公告)日：2011-02-15

申请号：US11910735

申请日：2006-04-14

申请人： Fengyi Jiang ,  Wenqing Fang ,  Li Wang ,  Chunlan Mo ,  Hechu Liu ,  Maoxing Zhou

发明人： Fengyi Jiang ,  Wenqing Fang ,  Li Wang ,  Chunlan Mo ,  Hechu Liu ,  Maoxing Zhou

IPC分类号： H01L29/06 ,  H01L21/203

CPC分类号： H01L33/007 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/78 ,  H01L33/0095

摘要： There is provided a method of fabricating InGaAlN film on a silicon substrate, which comprises the following steps of forming a pattern structured having grooves and mesas on the silicon substrate, and depositing InGaAlN film on the surface of substrate, wherein the depth of the grooves is more than 6 nm, and the InGaAlN film formed on the mesas of both sides of the grooves are disconnected in the horizontal direction. The method may grow high quality, no crack and large area of InGaAlN film by simply treating the substrate. At the same time, there is also provided a method of fabricating InGaAlN light-emitting device by using the silicon substrate.

摘要翻译： 提供了一种在硅衬底上制造InGaAlN膜的方法，其包括以下步骤：在硅衬底上形成具有凹槽和台面的图案，并在衬底表面上沉积InGaAlN膜，其中凹槽的深度为 大于6nm，并且形成在槽的两侧的台面上的InGaAlN膜在水平方向上断开。 该方法可以通过简单地处理基板来生长高质量，无裂纹和大面积的InGaAlN膜。 同时，还提供了通过使用硅衬底制造InGaAlN发光器件的方法。

公开(公告)号：US08431475B2

公开(公告)日：2013-04-30

申请号：US12159835

申请日：2007-08-31

申请人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

发明人： Fengyi Jiang ,  Li Wang ,  Wenqing Fang ,  Chunlan Mo

IPC分类号： H01L33/40

CPC分类号： H01L33/0095 ,  H01L33/32 ,  H01L33/40

摘要： One embodiment of the present invention provides a method for fabricating a group III-V nitride structure with an ohmic-contact layer. The method involves fabricating a group III-V nitride structure with a p-type layer. The method further involves depositing an ohmic-contact layer on the p-type layer without first annealing the p-type layer. The method also involves subsequently annealing the p-type layer and the ohmic-contact layer in an annealing chamber at a predetermined temperature for a predetermined period of time, thereby reducing the resistivity of the p-type layer and the ohmic contact in a single annealing process.

摘要翻译： 本发明的一个实施例提供了一种用欧姆接触层制造III-V族氮化物结构的方法。 该方法包括用p型层制造III-V族氮化物结构。 该方法还包括在p型层上沉积欧姆接触层，而不首先退火p型层。 该方法还包括随后在预定温度下在退火室中退火预定时间段内的p型层和欧姆接触层，从而降低单一退火中p型层的电阻率和欧姆接触 处理。

公开(公告)号：US20110298005A1

公开(公告)日：2011-12-08

申请号：US12680261

申请日：2007-10-12

申请人： Fengyi Jiang ,  Li Wang ,  Chunlan Mo ,  Wenqing Fang

发明人： Fengyi Jiang ,  Li Wang ,  Chunlan Mo ,  Wenqing Fang

IPC分类号： H01L33/02 ,  H01L21/20

CPC分类号： H01L21/02576 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/007

摘要： A method for fabricating a group III-V n-type nitride structure comprises fabricating a growth Si substrate and then depositing a group III-V n-type layer above the Si substrate using silane gas (SiH4) as a precursor at a flow rate set to a first predetermined value (210). Subsequently, the SiH4 flow rate is reduced to a second predetermined value during the fabrication of the n-type layer (220). The method also comprises forming a multi-quantum-well active region above the n-type layer. In addition, the flow rate is reduced over a predetermined period of time, and the second predetermined value is reached at a predetermined, sufficiently small distance from the interface between the n-type layer and the active region (230).

摘要翻译： 制造III-V族氮化物结构的方法包括制造生长Si衬底，然后使用硅烷气体（SiH 4）作为前体以流量设定在Si衬底上沉积III-V族III型层 到第一预定值（210）。 随后，在制造n型层（220）期间，将SiH 4流量减小到第二预定值。 该方法还包括在n型层上形成多量子阱有源区。 此外，在预定时间段内减小流量，并且在与n型层和有源区域（230）之间的界面预定的足够小的距离处达到第二预定值。

公开(公告)号：US20110133159A1

公开(公告)日：2011-06-09

申请号：US13059400

申请日：2008-08-19

申请人： Fengyi Jiang ,  Yingwen Tang ,  Chunlan Mo ,  Li Wang

发明人： Fengyi Jiang ,  Yingwen Tang ,  Chunlan Mo ,  Li Wang

IPC分类号： H01L33/06 ,  H01L33/44

CPC分类号： H01L33/145 ,  H01L33/0079 ,  H01L33/44

摘要： A semiconductor light-emitting device includes a substrate, a first doped semiconductor layer, a second doped semiconductor layer situated above the first doped semiconductor layer, and a multi-quantum-well (MQW) active layer situated between the first and the second doped layers. The device also includes a first electrode coupled to the first doped semiconductor layer, wherein part of the first doped semiconductor layer is passivated, and wherein the passivated portion of the first doped semiconductor layer substantially insulates the first electrode from the edges of the first doped semiconductor layer, thereby reducing surface recombination. The device further includes a second electrode coupled to the second doped semiconductor layer and a passivation layer which substantially covers the sidewalls of the first and second doped semiconductor layers, the MQW active layer, and part of the horizontal surface of the second doped semiconductor layer which is not covered by the second electrode.

摘要翻译： 半导体发光器件包括衬底，第一掺杂半导体层，位于第一掺杂半导体层上方的第二掺杂半导体层以及位于第一和第二掺杂层之间的多量子阱（MQW）有源层 。 该器件还包括耦合到第一掺杂半导体层的第一电极，其中部分第一掺杂半导体层被钝化，并且其中第一掺杂半导体层的钝化部分使第一电极与第一掺杂半导体层的边缘基本绝缘 层，从而减少表面复合。 该器件还包括耦合到第二掺杂半导体层的第二电极和基本上覆盖第一和第二掺杂半导体层，MQW有源层和第二掺杂半导体层的水平表面的一部分的侧壁的钝化层， 不被第二电极覆盖。