公开(公告)号：US20090295421A1

公开(公告)日：2009-12-03

申请号：US12473348

申请日：2009-05-28

申请人： Dae-Kyeun Kim

发明人： Dae-Kyeun Kim

IPC分类号： G01R31/26 ,  H01L23/544 ,  H01L21/3205

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are a test pattern of a semiconductor device, a method of manufacturing the same, and a method of testing the device using the test pattern. The test pattern includes a lower metal pattern part formed over a semiconductor substrate, an intermetal insulating film formed over the lower metal pattern part, and upper metal pattern test parts formed over the intermetal insulating film such that the upper metal pattern parts are separated from each other by a designated distance.

摘要翻译： 公开了半导体器件的测试图案，其制造方法以及使用测试图案测试器件的方法。 测试图案包括形成在半导体衬底上的下金属图形部分，形成在下金属图案部分上的金属间绝缘膜和形成在金属间绝缘膜上的上金属图案测试部分，使得上金属图案部分与每个 另外指定的距离。

公开(公告)号：US20090159980A1

公开(公告)日：2009-06-25

申请号：US12337511

申请日：2008-12-17

申请人： Dae Kyeun Kim

发明人： Dae Kyeun Kim

IPC分类号： H01L21/762 ,  H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/76232 ,  H01L21/823878

摘要： A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a conductive well formed by implanting a first conductive impurity into a semiconductor substrate, a device isolation film on one side of the conductive well, and an insulating region below the device isolation film and including the first conductive impurity and a second conductive impurity. The semiconductor device has the insulating region below the device isolation film, making it possible to prevent a short circuit generated between devices.

摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件包括通过将第一导电杂质注入半导体衬底，在导电阱的一侧上的器件隔离膜和器件隔离膜下面的绝缘区域形成的导电阱，并且包括第一导电杂质和第二导电 不纯。 半导体器件具有在器件隔离膜下面的绝缘区域，使得可以防止器件之间产生的短路。

公开(公告)号：US20090140375A1

公开(公告)日：2009-06-04

申请号：US12326903

申请日：2008-12-03

申请人： Dae-Kyeun Kim

发明人： Dae-Kyeun Kim

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76232

摘要： A semiconductor device can include a semiconductor substrate, a first trench formed in the semiconductor substrate, a second trench formed in the semiconductor substrate, a first device isolation layer formed in the first trench, a second device isolation layer formed in the second trench having a different structure than the first device isolation layer.

摘要翻译： 半导体器件可以包括半导体衬底，形成在半导体衬底中的第一沟槽，形成在半导体衬底中的第二沟槽，形成在第一沟槽中的第一器件隔离层，形成在第二沟槽中的第二器件隔离层， 不同于第一个器件隔离层的结构。

公开(公告)号：US07473627B2

公开(公告)日：2009-01-06

申请号：US11502060

申请日：2006-08-09

申请人： Dae Kyeun Kim ,  Jeong Ho Park

发明人： Dae Kyeun Kim ,  Jeong Ho Park

IPC分类号： H01L21/3205

CPC分类号： H01L27/11 ,  H01L21/76897

摘要： A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; forming a second insulating pattern over the substrate; forming a first salicide on an exposed portion of the substrate and a second salicide on an entire upper surface of the second conductive pattern; depositing a third insulating layer over the substrate, and etching selectively the third insulating layer to forming first and second contact holes exposing the first and second salicides. The method provides processing margin and prevents excessive etching of a conductive layer under the salicide, even if misalignment of an overlying contact hole happens.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成第一绝缘图案，第一导电图案和第二导电图案; 在第一绝缘图案，第一导电图案和第二导电图案的侧壁上形成间隔物; 在所述衬底上形成第二绝缘图案; 在所述基板的暴露部分上形成第一自对准硅化物，在所述第二导电图案的整个上表面上形成第二硅化物; 在衬底上沉积第三绝缘层，并且选择性地蚀刻第三绝缘层以形成暴露第一和第二杀液体的第一和第二接触孔。 该方法即使发生上覆接触孔的未对准，也提供了处理余量，并且防止了自对准硅衬底下的导电层的过度蚀刻。

公开(公告)号：US06864126B2

公开(公告)日：2005-03-08

申请号：US10747830

申请日：2003-12-29

申请人： Dae Kyeun Kim

发明人： Dae Kyeun Kim

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/44

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L29/665

摘要： A method of manufacturing a semiconductor device with a transistor comprising an LDD region and a silicide layer is disclosed. The method may include forming a gate electrode on a substrate, forming a first preliminary source/drain region with shallow junction through an ion implantation process using the gate electrode as a mask, and forming a ILD pattern with contact holes on the substrate including the gate electrode, the contact holes exposing the top of the gate electrode and some part of the first preliminary source/drain region. The method may also include forming an expanded source/drain region through an ion implantation process using the ILD pattern as a mask, forming a silicide layer on the top of the gate electrode and the expanded source/drain region, and forming contact plugs by filling the contact holes with metal.

摘要翻译： 公开了一种制造具有包括LDD区和硅化物层的晶体管的半导体器件的方法。 该方法可以包括在衬底上形成栅电极，通过使用栅电极作为掩模的离子注入工艺形成具有浅结的第一初级源极/漏极区，以及在包括栅极的衬底上形成具有接触孔的ILD图案 电极，接触孔暴露出栅极电极的顶部和第一初级源极/漏极区域的一部分。 该方法还可以包括通过使用ILD图案作为掩模的离子注入工艺形成扩展的源极/漏极区域，在栅电极的顶部和扩展的源极/漏极区域上形成硅化物层，以及通过填充形成接触塞 接触孔用金属。

公开(公告)号：US07919375B2

公开(公告)日：2011-04-05

申请号：US12211123

申请日：2008-09-16

申请人： Dae-Kyeun Kim

发明人： Dae-Kyeun Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/32155 ,  H01L29/66606 ,  H01L29/66621 ,  H01L29/7834

摘要： A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor device and a method for manufacturing the device that may minimize overlap between an LDD region and a lower portion of the gate electrode. Minimizing overlap may maximize device performance and minimize the generation of defects between gate electrodes.

摘要翻译： 公开了一种用于制造能够防止LDD区域和栅电极的下部彼此重叠以实现期望的器件性能的器件的半导体器件和方法。 实施例涉及半导体器件和用于制造器件的方法，其可以最小化LDD区域和栅电极的下部之间的重叠。 最小化重叠可以最大化器件性能并最小化栅电极之间的缺陷的产生。

公开(公告)号：US20090134477A1

公开(公告)日：2009-05-28

申请号：US12277987

申请日：2008-11-25

申请人： Dae-Kyeun Kim

发明人： Dae-Kyeun Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28035 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device and a method of fabricating the same include a gate electrode formed over the silicon substrate, the gate electrode including low-concentration conductive impurity regions, a high-concentration conductive impurity region formed between the low-concentration conductive impurity regions and a first silicide layer formed over the high-concentration conductive impurity region, and contact electrodes including a first contact electrode connected electrically to the gate electrode and a second contact electrode connected electrically to source/drain regions. The first contact electrode contacts the uppermost surface of the gate electrode and a sidewall of the gate electrode. The gate electrode can be easily connected to the contact electrode, the high-concentration region can be disposed only on the channel region, making it possible to maximize overall performance of the semiconductor device.

摘要翻译： 半导体器件及其制造方法包括形成在硅衬底上的栅电极，栅电极包括低浓度导电杂质区，形成在低浓度导电杂质区之间的高浓度导电杂质区和第一 形成在高浓度导电杂质区域上的硅化物层，以及包括与栅电极电连接的第一接触电极和电连接到源/漏区的第二接触电极的接触电极。 第一接触电极接触栅电极的最上表面和栅电极的侧壁。 栅极电极可以容易地连接到接触电极，高浓度区域可以仅设置在沟道区域上，使得可以使半导体器件的整体性能最大化。

公开(公告)号：US07435669B2

公开(公告)日：2008-10-14

申请号：US11024678

申请日：2004-12-30

申请人： Dae Kyeun Kim

发明人： Dae Kyeun Kim

IPC分类号： H01L21/22

CPC分类号： H01L29/66598 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S438/923

摘要： A method of fabricating a transistor in a semiconductor device. A gate oxide layer and a gate are formed on a semiconductor substrate. An oxide layer and a silicon nitride layer are stacked on the substrate. The stacked oxide and silicon nitride layers are etched back to expose a surface of the substrate. The silicon nitride layer is removed to form a gate sidewall spacer. Impurity ions are implanted into the substrate through the exposed surface of the substrate.

摘要翻译： 一种在半导体器件中制造晶体管的方法。 在半导体衬底上形成栅氧化层和栅极。 在基板上层叠氧化物层和氮化硅层。 将层叠的氧化物和氮化硅层回蚀刻以暴露衬底的表面。 去除氮化硅层以形成栅极侧壁间隔物。 杂质离子通过衬底的暴露表面注入到衬底中。

公开(公告)号：US20070122952A1

公开(公告)日：2007-05-31

申请号：US11563394

申请日：2006-11-27

申请人： Dae Kyeun Kim

发明人： Dae Kyeun Kim

IPC分类号： H01L21/338 ,  H01L29/00

CPC分类号： H01L21/76232 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S438/926

摘要： A dummy gate may be formed over an isolation layer. A sidewall spacer may be formed next to the dummy gate. The dummy gate and the sidewall spacer may substantially cover or completely cover the edge of isolation layer that is adjacent to an active area of a silicon substrate. Damage to the isolation layer due to a contact hole etching may be prevented, even if there are misalignments.

摘要翻译： 可以在隔离层上形成伪栅极。 可以在虚拟栅极旁边形成侧壁间隔物。 虚拟栅极和侧壁间隔件可以基本上覆盖或完全覆盖与硅衬底的有源区域相邻的隔离层的边缘。 即使存在未对准，也可以防止由于接触孔蚀刻而导致的隔离层的损伤。

公开(公告)号：US07737499B2

公开(公告)日：2010-06-15

申请号：US11616276

申请日：2006-12-26

申请人： Dae Kyeun Kim

发明人： Dae Kyeun Kim

IPC分类号： H01L27/01 ,  H01L29/76

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

摘要： Embodiments relate to a SRAM, in which a well isolation method may be applied so that an N-well and a P-well are separated from each other and that well walls of opposite conductive types are formed on facing sides. Also, the active regions of NMOS and PMOS may be connected to each other and the contacts of a PMOS drain and an NMOS source may be united to one so that the contacts are moved to the active regions of wide parts. A size of the common contact may be one to two times the size of a contact defined by a design rule. The active region may have a round bent part. The common contacts are arranged to be asymmetrical with each other. Therefore, it may be possible to secure the process margins of the active regions and the contacts, to improve a leakage current characteristic, and to improve yield. Also, it may be possible to prevent the dislocation of the active region and to omit a conventional thermal treatment process so that it may be possible to simplify processes and to reduce manufacturing cost.

摘要翻译： 实施例涉及一种SRAM，其中可以应用阱隔离方法，使得N阱和P阱彼此分离，并且在相对侧上形成相反导电类型的阱壁。 此外，NMOS和PMOS的有源区可以彼此连接，并且PMOS漏极和NMOS源的触点可以结合到一个，使得触点移动到宽部件的有源区域。 公共接触件的尺寸可以是由设计规则定义的接触件的尺寸的一至两倍。 有源区域可以具有圆形弯曲部分。 共同的触点被布置为彼此不对称。 因此，可以确保有源区和触点的工艺余量，以提高漏电流特性，并提高产量。 此外，可以防止有源区的位错并省略常规的热处理工艺，从而可以简化工艺并降低制造成本。