公开(公告)号：US10283698B2

公开(公告)日：2019-05-07

申请号：US15666903

申请日：2017-08-02

申请人： Seung Pil Ko ,  Kiseok Suh ,  Kilho Lee ,  Daeeun Jeong

发明人： Seung Pil Ko ,  Kiseok Suh ,  Kilho Lee ,  Daeeun Jeong

IPC分类号： H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  H01L43/08 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12 ,  H01L23/485 ,  H01L23/532

摘要： A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.

公开(公告)号：US20160336509A1

公开(公告)日：2016-11-17

申请号：US15093994

申请日：2016-04-08

申请人： Daeeun JEONG ,  Yoonjong SONG ,  Hyunchul SHIN

发明人： Daeeun JEONG ,  Yoonjong SONG ,  Hyunchul SHIN

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  H01L21/02071 ,  H01L21/02266 ,  H01L21/31105 ,  H01L21/32131

摘要： A method of forming patterns includes forming an etch target layer on a substrate, patterning the etch target layer to form patterns, forming an insulating layer on sidewalls of the patterns using a first ion beam generated from a first ion source, and removing the insulating layer using a second ion beam generated from a second ion source, wherein each of the first and second ion sources includes an insulating source, and wherein the insulating source includes at least one of oxygen or nitrogen.

摘要翻译： 形成图案的方法包括在衬底上形成蚀刻目标层，图案化蚀刻目标层以形成图案，使用从第一离子源产生的第一离子束在图案的侧壁上形成绝缘层，以及去除绝缘层 使用从第二离子源产生的第二离子束，其中所述第一和第二离子源中的每一个包括绝缘源，并且其中所述绝缘源包括氧或氮中的至少一种。

公开(公告)号：US20160141490A1

公开(公告)日：2016-05-19

申请号：US14796022

申请日：2015-07-10

申请人： Hyunsung JUNG ,  Daeeun JEONG

发明人： Hyunsung JUNG ,  Daeeun JEONG

IPC分类号： H01L43/10 ,  H01L43/02

CPC分类号： H01L43/02 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a contact plug, which includes a first crystalline region and an amorphous region located on the first crystalline region, and a magnetic tunnel junction pattern located on the amorphous region of the contact plug.

摘要翻译： 提供一种磁存储器件及其形成方法。 磁存储器件包括接触插塞，其包括第一结晶区域和位于第一结晶区域上的非晶区域，以及位于接触插塞的非晶区域上的磁性隧道结图案。

公开(公告)号：US10199431B2

公开(公告)日：2019-02-05

申请号：US15648772

申请日：2017-07-13

申请人： Daeeun Jeong

发明人： Daeeun Jeong

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L23/528 ,  H01L23/522 ,  H01L43/12

摘要： A device that includes a magnetic memory device, includes a magnetic tunnel junction pattern on a substrate and a mask structure on the magnetic tunnel junction pattern. The mask structure includes a conductive pattern and a sacrificial pattern, where the conductive pattern is between the magnetic tunnel junction pattern and the sacrificial pattern, and the sacrificial pattern includes a material having an etch selectivity with respect to the conductive pattern. The device includes an upper contact plug in contact with a surface of the conductive pattern of the mask structure. The device includes a lower interlayered insulating layer covering a cell region and a peripheral circuit region of the substrate, where the lower interlayered insulating layer on the cell region has a recessed top surface between adjacent magnetic tunnel junction patterns.

公开(公告)号：US20180197914A1

公开(公告)日：2018-07-12

申请号：US15648772

申请日：2017-07-13

申请人： Daeeun JEONG

发明人： Daeeun JEONG

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： A device that includes a magnetic memory device, includes a magnetic tunnel junction pattern on a substrate and a mask structure on the magnetic tunnel junction pattern. The mask structure includes a conductive pattern and a sacrificial pattern, where the conductive pattern is between the magnetic tunnel junction pattern and the sacrificial pattern, and the sacrificial pattern includes a material having an etch selectivity with respect to the conductive pattern. The device includes an upper contact plug in contact with a surface of the conductive pattern of the mask structure. The device includes a lower interlayered insulating layer covering a cell region and a peripheral circuit region of the substrate, where the lower interlayered insulating layer on the cell region has a recessed top surface between adjacent magnetic tunnel junction patterns.

公开(公告)号：US09954164B2

公开(公告)日：2018-04-24

申请号：US15588776

申请日：2017-05-08

申请人： Daeeun Jeong ,  Yoonjong Song

发明人： Daeeun Jeong ,  Yoonjong Song

IPC分类号： H01L21/00 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L43/08

摘要： Disclosed is a method for manufacturing a magnetic memory device. The method for manufacturing a magnetic memory device comprises sequentially forming a first magnetic layer, a tunnel barrier layer, and a second magnetic layer on a substrate, forming a boron absorption layer on the second magnetic layer, sequentially forming a metal capping layer and an oxygen donor layer on the boron absorption layer, and performing a heat treatment process to diffuse at least a portion of oxygen atoms included in the oxygen donor layer into the metal capping layer and the boron absorption layer. The metal capping layer has a greater oxygen diffusivity than the oxygen donor layer.

公开(公告)号：US20180068702A1

公开(公告)日：2018-03-08

申请号：US15603907

申请日：2017-05-24

申请人： Hyunsung Jung ,  DAEEUN JEONG

发明人： Hyunsung Jung ,  DAEEUN JEONG

IPC分类号： G11C11/16 ,  H01L43/02 ,  H01L43/08

CPC分类号： G11C11/1673 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a reference cell including a first resistance element and a second resistance element configured to be coupled in parallel to a second sensing node, the first resistance element including a first number of reference MTJs and the second resistance element including a second number of reference MTJs different from the first number of reference MTJs. The memory device further includes a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell. In some embodiments, the first number of reference MTJs includes first reference MTJs connected in series and the second number of reference MTJs includes second reference MTJs connected in series.

公开(公告)号：US20150035096A1

公开(公告)日：2015-02-05

申请号：US14319563

申请日：2014-06-30

申请人： SHINHEE HAN ,  DAEEUN JEONG ,  YONG KWAN KIM ,  YOONJONG SONG

发明人： SHINHEE HAN ,  DAEEUN JEONG ,  YONG KWAN KIM ,  YOONJONG SONG

IPC分类号： H01L43/02

CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228

摘要： Provided are a magnetic memory device and a method of fabricating the same. The device may include a cell selection device, a magnetic tunnel junction (MTJ), and a lower electrode connecting them. The lower electrode may include a vertical portion and a horizontal portion laterally extending from a side surface of the vertical portion. In the lower electrode, the vertical portion has a top surface higher than the horizontal portion and has a top surface including at least two parallel sides and other side at an angle thereto. The MTJ may be provided on the vertical portion of the lower electrode.

摘要翻译： 提供一种磁存储器件及其制造方法。 该装置可以包括细胞选择装置，磁性隧道结（MTJ）和连接它们的下部电极。 下电极可以包括从垂直部分的侧表面横向延伸的垂直部分和水平部分。 在下部电极中，垂直部分具有高于水平部分的顶表面，并且具有包括至少两个平行边和与其成一定角度的另一侧的顶表面。 MTJ可以设置在下电极的垂直部分上。

公开(公告)号：US10163478B2

公开(公告)日：2018-12-25

申请号：US15603907

申请日：2017-05-24

申请人： Hyunsung Jung ,  Daeeun Jeong

发明人： Hyunsung Jung ,  Daeeun Jeong

IPC分类号： G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a reference cell including a first resistance element and a second resistance element configured to be coupled in parallel to a second sensing node, the first resistance element including a first number of reference MTJs and the second resistance element including a second number of reference MTJs different from the first number of reference MTJs. The memory device further includes a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell. In some embodiments, the first number of reference MTJs includes first reference MTJs connected in series and the second number of reference MTJs includes second reference MTJs connected in series.

公开(公告)号：US20180198059A1

公开(公告)日：2018-07-12

申请号：US15666903

申请日：2017-08-02

申请人： Seung Pil KO ,  Kiseok SUH ,  Kilho LEE ,  Daeeun JEONG

发明人： Seung Pil KO ,  Kiseok SUH ,  Kilho LEE ,  Daeeun JEONG

IPC分类号： H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  H01L43/08 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12

CPC分类号： H01L43/02 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

摘要： A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.