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    DATA STORAGE DEVICES AND METHODS FOR MANUFACTURING THE SAME
    2.
    发明申请
    DATA STORAGE DEVICES AND METHODS FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20170324025A1

    公开(公告)日：2017-11-09

    申请号：US15436757

    申请日：2017-02-17

    申请人： KILHO LEE ,  Kiseok SUH ,  Yoonsung HAN ,  GWANHYEOB KOH ,  YOONJONG SONG

    发明人： KILHO LEE ,  Kiseok SUH ,  Yoonsung HAN ,  GWANHYEOB KOH ,  YOONJONG SONG

    IPC分类号： H01L43/02 ,  H01L43/12

    CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L43/12

    摘要： A data storage device and a method for manufacturing the data storage device provide a data storage device having a superior reliability and easy fabrication. The data storage device comprises a substrate including cell and peripheral circuit regions, a first conductive line on the peripheral circuit region, a peripheral contact plug between the substrate and the first conductive line, the peripheral contact plug being in contact with the first conductive line, a second conductive line on the cell region, a plurality of data storage structures between the substrate and the second conductive line, and a wiring structure between the substrate and each of the data storage structures and between the substrate and the peripheral contact plug. The first conductive line includes a bottom surface having a position from the substrate that is lower than a position of a bottom surface of the second conductive line.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180159023A1

    公开(公告)日：2018-06-07

    申请号：US15622064

    申请日：2017-06-13

    申请人： Kiseok SUH ,  BYOUNGJAE BAE ,  GWANHYEOB KOH ,  YOONJONG SONG ,  KILHO LEE

    发明人： Kiseok SUH ,  BYOUNGJAE BAE ,  GWANHYEOB KOH ,  YOONJONG SONG ,  KILHO LEE

    IPC分类号： H01L43/02 ,  H01L43/08 ,  H01L27/22

    CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

    摘要： A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20160086882A1

    公开(公告)日：2016-03-24

    申请号：US14791812

    申请日：2015-07-06

    申请人： Jaekyu LEE ,  Kiseok SUH

    发明人： Jaekyu LEE ,  Kiseok SUH

    IPC分类号： H01L23/528 ,  H01L23/535

    CPC分类号： H01L23/535 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.

    摘要翻译： 半导体存储器件包括在沟槽中的器件隔离，其限定彼此间隔开并且具有平行于第一方向的长轴的第一至第三有源图案，第一和第二字线沿垂直于第一方向的第二方向延伸 方向，位线和源线。 第一和第二活动图案被布置在第二方向上以构成列。 第三个活动模式位于列的一侧。 第一字线与第一和第二活动模式相交。 第二个字线与第三个活动模式相交。 当从平面图观察时，位线在第一和第三有源图案之间沿第一方向延伸，并且源极线在第二和第三有源图案之间沿第一方向延伸。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20170110507A1

    公开(公告)日：2017-04-20

    申请号：US15187929

    申请日：2016-06-21

    申请人： Kiseok SUH ,  Gwanhyeob Koh ,  Yoonjong Song

    发明人： Kiseok SUH ,  Gwanhyeob Koh ,  Yoonjong Song

    IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

    CPC分类号： H01L27/228 ,  H01L28/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    摘要： A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other. An isolation pattern is on the active region and the isolation region. The isolation pattern is between the first and second cell interconnection structures. Contact structures are between the first and second cell interconnection structures. The contact structures are at both sides of the isolation pattern and overlap the active region. Insulating patterns are between the first and second cell interconnection structures. The insulating patterns are at both sides of the isolation pattern and overlap the isolation region. Common source regions are under the first and second cell interconnection structures. The common source regions are in the active region. An isolating gate pattern that has a line shape is under the isolation pattern.

    VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    8.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    可变电阻存储器件及其制造方法

    公开(公告)号：US20120220087A1

    公开(公告)日：2012-08-30

    申请号：US13396658

    申请日：2012-02-15

    申请人： Kiseok SUH

    发明人： Kiseok SUH

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/105 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

    摘要： A variable resistance memory device includes a substrate having a cell array region and a peripheral circuit region, an epitaxial semiconductor layer on the cell array region and the peripheral circuit region, and a peripheral transistor whose channel region is constituted by the epitaxial semiconductor layer on the peripheral circuit region. The peripheral transistor is formed by forming a gate electrode structure on the epitaxial semiconductor layer, and implanting impurities into the epitaxial semiconductor layer to form a source/drain region.

    摘要翻译： 一种可变电阻存储器件，包括具有单元阵列区域和外围电路区域的基板，单元阵列区域和外围电路区域上的外延半导体层，以及外围晶体管，沟道区域由外延半导体层 外围电路区域。 通过在外延半导体层上形成栅电极结构，并将杂质注入外延半导体层以形成源极/漏极区，形成外围晶体管。