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公开(公告)号：US07421689B2
公开(公告)日：2008-09-02
申请号：US10695267
申请日：2003-10-28
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。
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公开(公告)号：US20050091652A1
公开(公告)日：2005-04-28
申请号：US10695267
申请日：2003-10-28
申请人： Jonathan Ross , Dale Morris , Donald Soltis , Rohit Bhatia , Eric Delano
发明人： Jonathan Ross , Dale Morris , Donald Soltis , Rohit Bhatia , Eric Delano
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。
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3.发明授权公开(公告)号：US06591360B1
公开(公告)日：2003-07-08
申请号：US09484138
申请日：2000-01-18
申请人： Donald C. Soltis, Jr. , Rohit Bhatia , Mark Gibson
发明人： Donald C. Soltis, Jr. , Rohit Bhatia , Mark Gibson
IPC分类号： G06F930
CPC分类号： G06F9/3838 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3867
摘要： A method and apparatus that generates a simplified, localized version (“a local stall”) of a global stall to improve the performance of a pipelined microprocessor. The local stall is generated when a data-dependency hazard is detected for a local consumer. Utilizing circuitry used in the pipelined microprocessor's data-forwarding circuitry, the local stall is generated with a relatively minor increase in circuitry. The local stall is generated much sooner than the global stall, arriving much sooner in a local pipeline. The local pipeline utilizes the local stall to override the global stall, when appropriate, and to ensure that correct data is read for a local consumer and to operate more efficiently than a standard pipeline without a local stall.
摘要翻译： 一种产生全局失速的简化的局部版本（“局部失速”）以改进流水线微处理器的性能的方法和装置。 当本地消费者检测到数据依赖性危险时，会产生本地摊位。 利用流水线微处理器的数据转发电路中使用的电路，产生局部失速，电路相对较小。 当地的摊位比全球摊位早得多，早在一个地方管道中就快到了。 当地管道利用本地摊位在适当的时候覆盖全局摊位，并确保为当地消费者读取正确的数据，并且比没有本地摊位的标准流水线更有效地运行。
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4.发明授权Using thread urgency in determining switch events in a temporal multithreaded processor unit 失效使用线程紧急性来确定时间多线程处理器单元中的切换事件公开(公告)号：US07213134B2
公开(公告)日：2007-05-01
申请号：US10092670
申请日：2002-03-06
IPC分类号： G06F9/48
CPC分类号： G06F9/3851
摘要： A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with its program instructions. The processing unit has a thread switch controller to monitor processing of instructions through the various pipelines. The thread controller also controls switch events to move from one thread to another within the pipelines. The controller may modify the urgency of any thread such as by issuing an additional instruction. The thread controller preferably utilizes certain heuristics in making switch event decisions. A time slice expiration unit may also monitor expiration of threads for a given time slice.
摘要翻译： 本发明的处理单元具有用于处理多线程指令的多条指令流水线。 每个线程可能具有与其程序指令相关联的紧急性。 处理单元具有线程开关控制器，用于监视通过各种管线的指令处理。 线程控制器还控制开关事件在管道内从一个线程移动到另一个线程。 控制器可以通过发出附加指令来修改任何线程的紧急性。 螺纹控制器优选地在确定开关事件决定时利用某些启发式。 时间片过期单元还可以监视给定时间片的线程的到期时间。
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公开(公告)号：US07930539B2
公开(公告)日：2011-04-19
申请号：US10910652
申请日：2004-08-03
CPC分类号： G06F21/6281 , G06F2221/2105
摘要： In a computer system including a plurality of resources, a device receives a request from a software program to access a specified one of the plurality of resources, determines whether the specified one of the plurality of resources is a protected resource. If the specified one of the plurality of resources is a protected resource, the device denies the request if the computer system is operating in a protected mode of operation, and processes the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.
摘要翻译： 在包括多个资源的计算机系统中，设备接收来自软件程序的访问多个资源中指定的一个资源的请求，确定多个资源中指定的一个资源是否是受保护的资源。 如果多个资源中的指定的资源是受保护的资源，则如果计算机系统在受保护的操作模式下操作，则设备拒绝该请求，并且如果计算机系统是 不工作在受保护的操作模式。
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公开(公告)号：US20070067602A1
公开(公告)日：2007-03-22
申请号：US11228058
申请日：2005-09-16
申请人： James Callister , Eric Delano , Rohit Bhatia , Shawn Walker , Mark Gibson
发明人： James Callister , Eric Delano , Rohit Bhatia , Shawn Walker , Mark Gibson
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0842
摘要： Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
摘要翻译： 描述了与减轻上下文切换高速缓存和TLB未命中的影响相关联的系统，方法，媒体和其他实施例。 一个示例性系统实施例包括被配置为运行多处理虚拟存储器操作系统的处理器。 处理器可以可操作地连接到存储器，并且可以包括被配置为存储TLB条目的高速缓存和翻译后备缓冲器（TLB）。 示例性系统可以包括上下文控制逻辑，其被配置为选择性地将数据从TLB复制到数据存储器，用于从处理器交换出的第一进程，并且将数据从数据存储选择性地复制到TLB，以将第二进程交换到 到处理器。
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7.发明申请Resource protection in a computer system with direct hardware resource access 审中-公开具有直接硬件资源访问的计算机系统中的资源保护公开(公告)号：US20060031672A1
公开(公告)日：2006-02-09
申请号：US10910630
申请日：2004-08-03
申请人： Donald Soltis , Rohit Bhatia , Eric DeLano , Bill Greene , Amy Santoni
发明人： Donald Soltis , Rohit Bhatia , Eric DeLano , Bill Greene , Amy Santoni
IPC分类号： H04L9/00
CPC分类号： G06F21/6281 , G06F12/1027 , G06F12/1491 , G06F2221/2105
摘要： In one embodiment of the present invention, a computer-implemented method is provided for use in a computer system including a plurality of resources. The plurality of resources include protected resources and unprotected resources. The unprotected resources include critical resources and non-critical resources. The method includes steps of: (A) receiving a request from a software program to access a specified one of the unprotected resources; (B) granting the request if the computer system is operating in a non-protected mode of operation; and (C) if the computer system is operating in a protected mode of operation, performing a step of denying the request if the computer system is not operating in a protected diagnostic mode of operation.
摘要翻译： 在本发明的一个实施例中，提供了一种在包括多个资源的计算机系统中使用的计算机实现的方法。 多个资源包括受保护的资源和不受保护的资源。 未受保护的资源包括关键资源和非关键资源。 该方法包括以下步骤：（A）从软件程序接收访问指定的一个未受保护的资源的请求; （B）如果计算机系统以非保护操作模式运行，则授予请求; 以及（C）如果所述计算机系统以受保护的操作模式操作，则如果所述计算机系统未在受保护的诊断操作模式下操作，则执行拒绝所述请求的步骤。
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公开(公告)号：US20060031679A1
公开(公告)日：2006-02-09
申请号：US10910652
申请日：2004-08-03
申请人： Donald Soltis , Rohit Bhatia , Eric DeLano
发明人： Donald Soltis , Rohit Bhatia , Eric DeLano
IPC分类号： H04L9/00
CPC分类号： G06F21/6281 , G06F2221/2105
摘要： In a computer system including a plurality of resources, techniques are disclosed for receiving a request from a software program to access a specified one of the plurality of resources, determining whether the specified one of the plurality of resources is a protected resource, and, if the specified one of the plurality of resources is a protected resource, for denying the request if the computer system is operating in a protected mode of operation, and processing the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.
摘要翻译： 在包括多个资源的计算机系统中，公开了用于接收来自软件程序的访问多个资源中的指定的资源的请求的技术，确定所述多个资源中的指定的一个资源是否是受保护的资源，以及如果 所述多个资源中的指定的一个资源是受保护的资源，如果所述计算机系统在受保护的操作模式下操作，则拒绝所述请求，以及如果所述计算机系统未运行，则基于与所述软件程序相关联的访问权限来处理所述请求 在受保护的操作模式下。
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公开(公告)号：US09348766B2
公开(公告)日：2016-05-24
申请号：US13994690
申请日：2011-12-21
申请人： Adi Basel , Gur Hildesheim , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
发明人： Adi Basel , Gur Hildesheim , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.
摘要翻译： 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。
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公开(公告)号：US09069690B2
公开(公告)日：2015-06-30
申请号：US13613777
申请日：2012-09-13
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/1027 , G06F2212/1024 , G06F2212/651 , G06F2212/655 , G06F2212/681 , G06F2212/684
摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并且从寻呼结构获得物理地址的对应部分，与第一步行者并行操作的第二步行者，以及 用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼高速缓存器中的逻辑。 描述和要求保护其他实施例。
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