公开(公告)号：US07849465B2

公开(公告)日：2010-12-07

申请号：US11134687

申请日：2005-05-19

Applicant: Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

Inventor： Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

IPC: G06F9/46 ,  G06F13/24 ,  G06F7/38

CPC classification number: G06F9/3851 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

Abstract translation: 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。

公开(公告)号：US20090070562A1

公开(公告)日：2009-03-12

申请号：US12267394

申请日：2008-11-07

Applicant: David W. BURNS ,  James D. ALLEN ,  Michael D. UPTON ,  Darrell D. BOGGS ,  David J. SAGER

Inventor： David W. BURNS ,  James D. ALLEN ,  Michael D. UPTON ,  Darrell D. BOGGS ,  David J. SAGER

IPC: G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/3851

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract translation: 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

公开(公告)号：US06467027B1

公开(公告)日：2002-10-15

申请号：US09475746

申请日：1999-12-30

Applicant: Alan B. Kyker ,  Darrell D. Boggs

Inventor： Alan B. Kyker ,  Darrell D. Boggs

IPC: G06F1200

CPC classification number: G06F9/3812 ,  G06F12/0875

Abstract: A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.

Abstract translation: 一种用于使用使用字段来维护在流水线处理器中的指令的方法。 该方法包括接收对指令的读取请求，响应于读取请求发送指令并设置与该指令相关联的使用字段以使用。 该方法的替代实施例涉及响应于读请求发送指令，接收指令退出通知并重置ITLB中的使用字段。 该方法也可以用在ICACHE中，其中使用字段与存储在ICACHE中的每个指令相关联。 该方法的其他实施例可以在ITLB和ICACHE中同时使用作为资源跟踪机制来维护资源。

公开(公告)号：US5463745A

公开(公告)日：1995-10-31

申请号：US174074

申请日：1993-12-22

Applicant: Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

Inventor： Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: Instructions are fetched and issued by an instruction fetch and issue circuit with the instructions' sizes in program order. An allocate circuit allocates reservation station entries in a reservation station circuit, and reorder buffer entries in a reorder circuit, for the issued instructions in order, storing the instructions' sizes in the allocated reorder buffer entries. The reservation and dispatch circuit dispatches the issued instructions to the execution circuits for execution when they are ready. The execution circuits store the result data including target addresses of branch instructions into the corresponding reorder buffer entries. During each retirement operation, a retire circuit reads the instruction sizes and the target addresses for a predetermined number of issued instructions from their allocated reorder buffer entries. The retire circuit determines two or more speculative next instruction pointers for each of the issued instructions, factoring into consideration whether the issued instructions are branch instructions or not, and their relative positions to each other. Each of the speculative next instruction pointers indicates what the next instruction pointer for the processor should be for retiring a particular combination of the result data values of the issued instructions under consideration. The retire circuit conditionally updates the next instruction pointer with one of the speculative next instruction pointers, depending on how many, if any, of the instructions can actually retire, and whether any of the actually retiring instructions are branch instructions.

Abstract translation: 指令由指令提取和发布电路以指令的大小以程序顺序取出并发出。 分配电路在保留站电路中分配保留站条目，并且重新排序重新排序电路中的缓冲区条目，以便按顺序发布指令，将指令的大小存储在所分配的重排序缓冲器条目中。 预约和调度电路在准备就绪时将发出的指令发送到执行电路执行。 执行电路将包括分支指令的目标地址的结果数据存储到相应的重排序缓冲器条目中。 在每个退休操作期间，退出电路从其分配的重排序缓冲器条目读取预定数量的已发布指令的指令大小和目标地址。 退出电路为每个发出的指令确定两个或更多个推测下一个指令指针，考虑所发出的指令是否是分支指令，以及它们彼此的相对位置。 每个推测下一个指令指针指示处理器的下一个指令指针应该用于退出所考虑的已发出指令的结果数据值的特定组合。 退出电路有条件地使用推测下一个指令指针之一更新下一个指令指针，这取决于指令实际可以退出多少（如果有的话），以及是否有任何实际退出的指令是分支指令。

公开(公告)号：US07219349B2

公开(公告)日：2007-05-15

申请号：US10792154

申请日：2004-03-02

Applicant: Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

Inventor： Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

IPC: G06F9/46 ,  G06F9/40 ,  G06F15/76

CPC classification number: G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3869

Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

Abstract translation: 提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。 重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。 在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。 通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

公开(公告)号：US06981129B1

公开(公告)日：2005-12-27

申请号：US09705668

申请日：2000-11-02

Applicant: Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

Inventor： Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/3861

Abstract: Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Abstract translation: 使用重新安排的重播队列在处理器中重新播放依赖循环。 所述处理器包括用于接收多个指令的重放队列，以及执行所述多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。 当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。 检查器耦合到执行单元以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

公开(公告)号：US06799268B1

公开(公告)日：2004-09-28

申请号：US09607640

申请日：2000-06-30

Applicant: Darrell D. Boggs ,  Shlomit Weiss ,  Alan Kyker

Inventor： Darrell D. Boggs ,  Shlomit Weiss ,  Alan Kyker

IPC: G06F938

CPC classification number: G06F9/384 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

Abstract: A branch ordering buffer. One disclosed apparatus includes a processor state management circuit to maintain a primary state and a shadow state, each of the primary state and the shadow state including mappings from logical registers to physical registers. The primary state is a speculative state. This disclosed apparatus also includes a branch ordering circuit to prevent the shadow state from advancing beyond a branch instruction until commitment of the branch instruction.

Abstract translation: 分支排序缓冲区。 一种公开的设备包括处理器状态管理电路，用于维持主状态和阴影状态，每个主状态和阴影状态包括从逻辑寄存器到物理寄存器的映射。 主要国家是投机国。 该公开的装置还包括分支排序电路，以防止阴影状态超出分支指令直到分支指令的承诺。

公开(公告)号：US5687338A

公开(公告)日：1997-11-11

申请号：US511296

申请日：1995-08-04

Applicant: Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Ashwani K. Gupta ,  Glenn J. Hinton ,  David B. Papworth

Inventor： Darrell D. Boggs ,  Robert P. Colwell ,  Michael A. Fetterman ,  Andrew F. Glew ,  Ashwani K. Gupta ,  Glenn J. Hinton ,  David B. Papworth

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3814 ,  G06F12/0897 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3863

Abstract: A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line. When the marker instruction is committed to architectural state, the victim cache entry specified by the marker is deallocated in the victim cache to permit storage of other instruction cache victims.

Abstract translation: 提供了一种用于处理器中的指令重写的方法和装置。 为了确保宏指令在处理器处理事件之后可用于重新获取指令，或者在分支错误预测之后确定正确的重新启动地址，指令存储器包括用于缓存要获取的宏指令的指令高速缓存，以及用于缓存受害者的受害缓存 从指令缓存。 为了确保可用的宏指令进行重写，指令存储器（指令高速缓存和受害器缓存在一起）总是存储可能需要重新引导的宏指令，直到宏指令提交到架构状态。 当指令高速缓存线受害时，标记微指令被插入到处理器流水线中。 标记指定受害缓存行占用的受害缓存中的条目。 当标记指令被提交到架构状态时，标记指定的受害者缓存条目被释放在受害缓存中，以允许存储其他指令缓存受害者。

公开(公告)号：US08850165B2

公开(公告)日：2014-09-30

申请号：US13155055

申请日：2011-06-07

Applicant: David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

Inventor： David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

IPC: G06F9/38 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/3851

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract translation: 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。

公开(公告)号：US20110239221A1

公开(公告)日：2011-09-29

申请号：US13155055

申请日：2011-06-07

Applicant: David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

Inventor： David W. Burns ,  James D. Allen ,  Michael D. Upton ,  Darrell D. Boggs ,  David J. Sager

IPC: G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/3851

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract translation: 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。