公开(公告)号：US07271091B2

公开(公告)日：2007-09-18

申请号：US11024467

申请日：2004-12-30

申请人： Date-Gun Lee

发明人： Date-Gun Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a metal pattern in a semiconductor device which is capable of reducing contact resistivity with an interconnection contact. The method includes forming a tungsten interconnection contact passing through a lower insulating layer on a semiconductor substrate, forming an upper insulating layer covering the interconnection contact, and forming a groove having the same line width as a damascene trench on the upper insulating layer. The method also includes forming a mask spacer on a sidewall of the groove, forming the damascene trench having an inclined bottom profile for exposing a top surface and a portion of a sidewall of the interconnection contact, and forming a metal pattern with which the damascene trench is filled, the metal pattern electrically connected to the interconnection contact.

摘要翻译： 一种在能够降低与互连接点的接触电阻率的半导体器件中形成金属图案的方法。 该方法包括形成通过半导体衬底上的下绝缘层的钨互连接触，形成覆盖互连接触的上绝缘层，并在上绝缘层上形成具有与镶嵌沟槽相同的线宽的沟槽。 该方法还包括在槽的侧壁上形成掩模间隔物，形成具有倾斜底部轮廓的镶嵌槽，用于暴露互连接触件的顶表面和侧壁的一部分，并形成金属图案，通过该金属图案，镶嵌槽 被填充，金属图形电连接到互连触点。

公开(公告)号：US20060014382A1

公开(公告)日：2006-01-19

申请号：US11181275

申请日：2005-07-13

申请人： Date-Gun Lee

发明人： Date-Gun Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L2221/1031

摘要： The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist layer filling the contact hole; removing the photoresist layer such that the first insulating layer is exposed and a recess is formed in the contact hole; reducing, removing or substantially eliminating the recess by removing an upper portion of the first insulating layer; forming a second insulating layer having a trench exposing the photoresist layer and a portion of the first insulating layer adjacent thereto; and removing the remaining photoresist layer.

摘要翻译： 当通过以下方法制造半导体器件时，可以增强镶嵌图案的CD均匀性和互连线的可靠性，所述方法包括：在半导体衬底上形成第一绝缘层，所述第一绝缘层具有部分地暴露衬底的接触孔; 形成填充所述接触孔的光致抗蚀剂层; 去除光致抗蚀剂层，使得第一绝缘层暴露并且在接触孔中形成凹部; 通过去除第一绝缘层的上部来减少，去除或基本上消除凹部; 形成具有暴露光致抗蚀剂层的沟槽和与其相邻的第一绝缘层的一部分的第二绝缘层; 并除去剩余的光致抗蚀剂层。

公开(公告)号：US20050142841A1

公开(公告)日：2005-06-30

申请号：US11024467

申请日：2004-12-30

申请人： Date-Gun Lee

发明人： Date-Gun Lee

IPC分类号： H01L21/283 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a metal pattern in a semiconductor device which is capable of reducing contact resistivity with an interconnection contact. The method includes forming a tungsten interconnection contact passing through a lower insulating layer on a semiconductor substrate, forming an upper insulating layer covering the interconnection contact, and forming a groove having the same line width as a damascene trench on the upper insulating layer. The method also includes forming a mask spacer on a sidewall of the groove, forming the damascene trench having an inclined bottom profile for exposing a top surface and a portion of a sidewall of the interconnection contact, and forming a metal pattern with which the damascene trench is filled, the metal pattern electrically connected to the interconnection contact.

摘要翻译： 一种在能够降低与互连接点的接触电阻率的半导体器件中形成金属图案的方法。 该方法包括形成通过半导体衬底上的下绝缘层的钨互连接触，形成覆盖互连接触的上绝缘层，并在上绝缘层上形成具有与镶嵌沟槽相同的线宽的沟槽。 该方法还包括在槽的侧壁上形成掩模间隔物，形成具有倾斜底部轮廓的镶嵌槽，用于暴露互连接触件的顶表面和侧壁的一部分，并形成金属图案，通过该金属图案，镶嵌槽 被填充，金属图形电连接到互连触点。

公开(公告)号：US07186644B2

公开(公告)日：2007-03-06

申请号：US11026984

申请日：2004-12-30

申请人： Date Gun Lee

发明人： Date Gun Lee

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76838

摘要： Methods of preventing oxidation of a copper interconnect of a semiconductor device are disclosed. An example method forms a lower copper interconnect on a substrate having at least one predetermined structure, deposits a nitride layer on the lower copper interconnect and on the substrate, and sequentially depositing a first insulating layer, an etch-stop layer, and a second insulating layer on the nitride layer. The example method also forms a trench and a via hole through the second insulating layer and the first insulating layer by using a dual damascene process, etches the nitride layer so as to expose some portion of the lower copper interconnect, and supplies combining gas onto the exposed portion of the lower copper interconnect.

摘要翻译： 公开了防止半导体器件的铜互连的氧化的方法。 一种示例性方法在具有至少一个预定结构的衬底上形成较低的铜互连，在下铜互连和衬底上沉积氮化物层，并依次沉积第一绝缘层，蚀刻停止层和第二绝缘层 层。 该示例性方法还通过使用双镶嵌工艺形成穿过第二绝缘层和第一绝缘层的沟槽和通孔，蚀刻氮化物层以暴露下部铜互连的一些部分，并将合并气体供应到 下部铜互连的露出部分。

公开(公告)号：US07307015B2

公开(公告)日：2007-12-11

申请号：US11181275

申请日：2005-07-13

申请人： Date-Gun Lee

发明人： Date-Gun Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L2221/1031

摘要： The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist layer filling the contact hole; removing the photoresist layer such that the first insulating layer is exposed and a recess is formed in the contact hole; reducing, removing or substantially eliminating the recess by removing an upper portion of the first insulating layer; forming a second insulating layer having a trench exposing the photoresist layer and a portion of the first insulating layer adjacent thereto; and removing the remaining photoresist layer.

摘要翻译： 当半导体器件通过以下方法制造半导体器件时，可以增强镶嵌图案的CD均匀性和互连线的可靠性：包括：在半导体衬底上形成第一绝缘层，第一绝缘层具有部分地暴露衬底的接触孔; 形成填充所述接触孔的光致抗蚀剂层; 去除光致抗蚀剂层，使得第一绝缘层暴露并且在接触孔中形成凹部; 通过去除第一绝缘层的上部来减少，去除或基本上消除凹部; 形成具有暴露光致抗蚀剂层的沟槽和与其相邻的第一绝缘层的一部分的第二绝缘层; 并除去剩余的光致抗蚀剂层。

公开(公告)号：US07183218B2

公开(公告)日：2007-02-27

申请号：US10734818

申请日：2003-12-12

申请人： Date-Gun Lee

发明人： Date-Gun Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/3085

摘要： The present invention relates to a fabrication method of a semiconductor device using EPD system, which enables uniform hole etching regardless of changes of etch rates of etching chemical and thickness of interlayer insulating layer after CMP, and the fabrication method comprises: forming a nitride layer on an interlayer insulating layer; forming a photoresist layer on the nitride layer, and exposing and developing the photoresist layer to form a photoresist pattern; etching the nitride layer using the photoresist pattern as a mask and contiguously etching the photoresist pattern and the interlayer insulating layer together; setting etch stop point as the point that the photoresist pattern is removed by etching and thus the nitride layer is exposed.

摘要翻译： 本发明涉及使用EPD系统的半导体器件的制造方法，其能够均匀地进行孔蚀刻，而不管蚀刻化学品的蚀刻速率和CMP之后的层间绝缘层的厚度如何变化，并且制造方法包括：在 层间绝缘层; 在所述氮化物层上形成光致抗蚀剂层，以及曝光和显影所述光致抗蚀剂层以形成光致抗蚀剂图案; 使用光致抗蚀剂图案作为掩模蚀刻氮化物层，并将光致抗蚀剂图案和层间绝缘层连续地蚀刻; 将蚀刻停止点设置为通过蚀刻去除光致抗蚀剂图案的点，从而暴露氮化物层。

公开(公告)号：US06995082B2

公开(公告)日：2006-02-07

申请号：US10722299

申请日：2003-11-25

申请人： Date-Gun Lee

发明人： Date-Gun Lee

IPC分类号： H01L21/302

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/4847 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48992 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00

摘要： The present invention relates to a bonding pad of a semiconductor device and a formation method thereof, and the object of the present invention is to prevent bonding defects by enlarging contact area between a bonding pad and a soldering material and to prevent moisture from penetrating into an oxide layer. The present invention provides a bonding pad of a semiconductor device comprising: a barrier metal layer formed on a structure of a semiconductor substrate; a metal wire layer formed on the barrier metal layer; a passivation metal layer formed on the metal wire layer and removed partly to expose a portion of the upper surface of the metal wire layer; an insulating layer which is formed on the passivation metal layer and has a contact hole exposing the metal wire layer via the portion that the passivation metal layer is removed; and an adhesive metal layer formed on the inner surface of the contact hole.

摘要翻译： 本发明涉及一种半导体器件的焊盘及其形成方法，其目的在于通过扩大接合焊盘与焊接材料之间的接触面积来防止焊接缺陷，并防止水分渗入 氧化层。 本发明提供一种半导体器件的焊盘，包括：形成在半导体衬底的结构上的阻挡金属层; 形成在阻挡金属层上的金属线层; 钝化金属层，形成在所述金属线层上，并部分地去除以暴露所述金属线层的上表面的一部分; 绝缘层，其形成在所述钝化金属层上并且具有通过去除所述钝化金属层的部分暴露所述金属线层的接触孔; 以及形成在接触孔的内表面上的粘合金属层。

公开(公告)号：US06972242B2

公开(公告)日：2005-12-06

申请号：US10741498

申请日：2003-12-19

申请人： Date-Gun Lee

发明人： Date-Gun Lee

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/762

CPC分类号： H01L21/3085 ,  H01L21/76224

摘要： Semiconductor device fabrication methods are disclosed. According to one example, a method includes forming a pad oxide layer and a nitride layer sequentially on a silicon substrate, and forming a photoresist pattern for trench formation on the nitride layer; etching the nitride layer and the pad oxide layer using the photoresist pattern as a mask while etching the silicon substrate to form a trench using the nitride layer as an etch stopper; filling the trench by depositing an oxide layer for trench gap filling on entire surface of the silicon substrate; and performing planarization which makes the gap filling oxide exist only in the trench.

摘要翻译： 公开了半导体器件制造方法。 根据一个示例，一种方法包括在硅衬底上依次形成衬垫氧化物层和氮化物层，并在氮化物层上形成用于沟槽形成的光致抗蚀剂图案; 使用光致抗蚀剂图案作为掩模蚀刻氮化物层和焊盘氧化物层，同时蚀刻硅衬底以使用氮化物层作为蚀刻停止层形成沟槽; 通过在硅衬底的整个表面上沉积用于沟槽间隙填充的氧化物层来填充沟槽; 并且进行使间隙填充氧化物仅存在于沟槽中的平坦化。