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公开(公告)号：US20130121504A1
公开(公告)日：2013-05-16
申请号：US13428496
申请日：2012-03-23
Applicant: Robert ADAMS , David HOSSACK , Benjamin VIGODA , Eric NESTLER , Mira WILCZEK
Inventor： Robert ADAMS , David HOSSACK , Benjamin VIGODA , Eric NESTLER , Mira WILCZEK
CPC classification number: H04R3/005 , H04R2499/13
Abstract: Microphone stages in a microphone array may be coupled together in a daisy chain. Each stage may include a microphone, an analog to digital converter, a decimation unit, a receiver, an adder, and a transmitter. The converter may convert analog audio microphone signals into digital codes that may be decimated. The adder may add decimated digital codes in each stage to a cumulative sum of decimated digital codes from prior stages. This new sum may be transmitted to the next microphone stage, where the adder may add the decimated digital codes from that stage to the cumulative sum. A serial interface may be used to connect the transmitters and receivers of each of the stages. The serial interface may be used to transmit the cumulative sum of decimated digital codes between the stages. The serial interface may also be used to transmit configuration data between the stages.
Abstract translation: 麦克风阵列中的麦克风级可以以菊花链耦合在一起。 每个阶段可以包括麦克风，模数转换器，抽取单元，接收器，加法器和发射器。 转换器可将模拟音频麦克风信号转换为可能被抽取的数字代码。 加法器可以将每个级中的抽取的数字代码添加到来自前一级的抽取的数字代码的累积和。 这个新的和可以传送到下一个麦克风阶段，其中加法器可以将从该阶段抽取的数字代码添加到累积和。 可以使用串行接口连接每个级的发射机和接收机。 串行接口可以用于在级之间传送抽取的数字代码的累加和。 串行接口也可用于在各个级之间传输配置数据。
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公开(公告)号：US09563851B2
公开(公告)日：2017-02-07
申请号：US13491212
申请日：2012-06-07
Applicant: Jeffrey Bernstein , Benjamin Vigoda , Kartik Nanda , Rishi Chaturvedi , David Hossack , William Peet , Andrew Schweitzer , Timothy Caputo
Inventor： Jeffrey Bernstein , Benjamin Vigoda , Kartik Nanda , Rishi Chaturvedi , David Hossack , William Peet , Andrew Schweitzer , Timothy Caputo
Abstract: In an aspect, in general, a programmable computation device performs computations of an inference task specified by a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. The device includes one or more processing elements. Each processing element includes a first storage for a definition of a factor, a second storage for data associated with the inputs and/or outputs of at least some of the computations, and one or more computation units coupled to the first storage and the second storage for performing a succession of parts of the at least some of the computations that are associated with a factor, the succession of parts defined by data in the storage for the definition of the factor.
Abstract translation: 一方面，通常，可编程计算装置执行由多个变量和多个因素指定的推理任务的计算，每个因子与变量的子集相关联。 该装置包括一个或多个处理元件。 每个处理元件包括用于定义因子的第一存储器，用于与至少一些计算的输入和/或输出相关联的数据的第二存储器以及耦合到第一存储器和第二存储器的一个或多个计算单元 用于执行与因素相关联的所述至少一些计算的一部分的连续的部分，所述部分由所述存储器中的数据由所述因子的定义定义的部分所定义。
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Patent Agency Ranking
公开(公告)号：US20140047293A1
公开(公告)日：2014-02-13
申请号：US13584630
申请日：2012-08-13
Applicant: David Lamb , Kendrick Owen Daniel Franzen , David Hossack
Inventor： David Lamb , Kendrick Owen Daniel Franzen , David Hossack
IPC: G01R31/3177
CPC classification number: G01R31/27 , G01R31/318555
Abstract: A semiconductor circuit comprising a digital circuit portion, which comprises a combinatorial logic block. The semiconductor circuit further comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion involves, using the scan chain, writing bit values to inputs of the individually addressable scan control registers, and reading bit values from at least one output of an individually addressable scan control register. The method and semiconductor circuit allow thorough testing and diagnosing of failing semiconductor devices, including core logic thereof, while mounted on a printed circuit board.
Abstract translation: 一种包括数字电路部分的半导体电路，其包括组合逻辑块。 半导体电路还包括扫描链，用于将预定义的数字测试图案加载并应用于组合逻辑块的输入。 双向通信端口适于将输入数据写入数字电路部分的地址空间。 扫描控制硬件包括被映射到双向通信端口的地址空间的多个单独可寻址的扫描控制寄存器。 测试数字电路部分的方法涉及使用扫描链将位数值写入单独寻址的扫描控制寄存器的输入，以及从单独寻址的扫描控制寄存器的至少一个输出读取位值。 该方法和半导体电路允许对安装在印刷电路板上的故障半导体器件（包括其核心逻辑）进行彻底的测试和诊断。
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公开(公告)号：US09121892B2
公开(公告)日：2015-09-01
申请号：US13584630
申请日：2012-08-13
Applicant: David Lamb , Kendrick Owen Daniel Franzen , David Hossack
Inventor： David Lamb , Kendrick Owen Daniel Franzen , David Hossack
IPC: G01R31/28 , G01R31/27 , G01R31/3185
CPC classification number: G01R31/27 , G01R31/318555
Abstract: A semiconductor circuit comprises a digital circuit portion, which in turn comprises a combinatorial logic block. The semiconductor circuit comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion such as register addresses and/or memory addresses. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion through the scan chain involves writing bit values to inputs of the individually addressable scan control registers and reading bit values from at least one output of an individually addressable scan control register.
Abstract translation: 半导体电路包括数字电路部分，该数字电路部分又包括组合逻辑块。 半导体电路包括扫描链，用于将预定义的数字测试图案加载并应用于组合逻辑块的输入。 双向通信端口适于将输入数据写入数字电路部分的地址空间，例如寄存器地址和/或存储器地址。 扫描控制硬件包括被映射到双向通信端口的地址空间的多个单独可寻址的扫描控制寄存器。 通过扫描链测试数字电路部分的方法涉及将位值写入到可单独寻址的扫描控制寄存器的输入和从单独寻址扫描控制寄存器的至少一个输出读取位值。
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5.发明申请Sigma-delta modulator with reduced switching rate for use in class-D amplification 有权具有降低的开关速率的Σ-Δ调制器用于D类放大公开(公告)号：US20050012649A1
公开(公告)日：2005-01-20
申请号：US10851400
申请日：2004-05-21
Applicant: Robert Adams , David Hossack , Eric Gaalaas
Inventor： Robert Adams , David Hossack , Eric Gaalaas
Abstract: A sigma delta modulator includes a modulator module that includes a quantizer with variable hysteresis, which receives an input signal to perform necessary modulation operations. A non-linear mapping module receives a signal associated with said input signal and tabulates the necessary hysteresis control information so as to reduce the transition rate of the modulator module.
Abstract translation: Σ-Δ调制器包括调制器模块，其包括具有可变迟滞的量化器，其接收输入信号以执行必要的调制操作。 非线性映射模块接收与所述输入信号相关联的信号并列出所需的滞后控制信息，以便降低调制器模块的转换速率。
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公开(公告)号：US09479866B2
公开(公告)日：2016-10-25
申请号：US13428496
申请日：2012-03-23
Applicant: Robert Adams , David Hossack , Benjamin Vigoda , Eric Nestler , Mira Wilczek
Inventor： Robert Adams , David Hossack , Benjamin Vigoda , Eric Nestler , Mira Wilczek
IPC: H04R3/00
CPC classification number: H04R3/005 , H04R2499/13
Abstract: Microphone stages in a microphone array may be coupled together in a daisy chain. Each stage may include a microphone, an analog to digital converter, a decimation unit, a receiver, an adder, and a transmitter. The converter may convert analog audio microphone signals into digital codes that may be decimated. The adder may add decimated digital codes in each stage to a cumulative sum of decimated digital codes from prior stages. This new sum may be transmitted to the next microphone stage, where the adder may add the decimated digital codes from that stage to the cumulative sum. A serial interface may be used to connect the transmitters and receivers of each of the stages. The serial interface may be used to transmit the cumulative sum of decimated digital codes between the stages. The serial interface may also be used to transmit configuration data between the stages.
Abstract translation: 麦克风阵列中的麦克风级可以以菊花链耦合在一起。 每个阶段可以包括麦克风，模数转换器，抽取单元，接收器，加法器和发射器。 转换器可将模拟音频麦克风信号转换为可能被抽取的数字代码。 加法器可以将每个级中的抽取的数字代码添加到来自前一级的抽取的数字代码的累积和。 这个新的和可以传送到下一个麦克风阶段，其中加法器可以将从该阶段抽取的数字代码添加到累积和。 可以使用串行接口连接每个级的发射机和接收机。 串行接口可以用于在级之间传送抽取的数字代码的累加和。 串行接口也可用于在各个级之间传输配置数据。
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公开(公告)号：US06924757B2
公开(公告)日：2005-08-02
申请号：US10851400
申请日：2004-05-21
Applicant: Robert W. Adams , David Hossack , Eric Gaalaas
Inventor： Robert W. Adams , David Hossack , Eric Gaalaas
Abstract: A sigma delta modulator includes a modulator module that includes a quantizer with variable hysteresis, which receives an input signal to perform necessary modulation operations. A non-linear mapping module receives a signal associated with said input signal and tabulates the necessary hysteresis control information so as to reduce the transition rate of the modulator module.
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