公开(公告)号：US06441436B1

公开(公告)日：2002-08-27

申请号：US09725094

申请日：2000-11-29

申请人： De-Yuan Wu ,  Chih-Cheng Liu

发明人： De-Yuan Wu ,  Chih-Cheng Liu

IPC分类号： H01L2701

CPC分类号： H01L27/10873 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/1203

摘要： A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

摘要翻译： 包括MOS晶体管和具有背栅极控制的改进的SOI衬底的SOI DRAM单元。 SOI衬底包括形成在衬底上的第一绝缘层，具有第一导电类型的第一半导体层，第二绝缘层和具有第一导电类型的第二半导体层。 MOS晶体管包括形成在第二半导体层上的栅极和形成在第二半导体层中的栅极的任一侧上的具有第二导电类型的源极和漏极区域，其中源极和漏极电连接到位线 和电容器。 第一氧化区域形成在源极区域下方的第一半导体层中，并且在漏极区域下方的第一半导体层中形成第二氧化区域。 第一氧化区域和第二氧化区域都与第二绝缘层邻接。

公开(公告)号：US06432827B1

公开(公告)日：2002-08-13

申请号：US09725027

申请日：2000-11-29

申请人： Sun-Chieh Chien ,  De-Yuan Wu ,  Yung-Chung Lin

发明人： Sun-Chieh Chien ,  De-Yuan Wu ,  Yung-Chung Lin

IPC分类号： H01L21461

CPC分类号： H01L21/31056 ,  H01L27/10897

摘要： The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

摘要翻译： 本发明提供了EDRAM的层间电介质的平面化方法。 该方法包括在EDRAM的半导体晶片上限定外围电路区域和存储器阵列区域，以及形成多个MOS晶体管和电容器。 同样，使用电容器的存储节点的布局图案作为反向掩模，在半导体晶片上形成电介质层和光致抗蚀剂层以进行蚀刻处理。 因此，存储器阵列区域中的光致抗蚀剂层的部分被去除，同时将存储器阵列区域中的介电层蚀刻预定深度。 最后，在电介质层上进行化学机械抛光工艺，以平坦化EDRAM的层间电介质。

公开(公告)号：US06271088B1

公开(公告)日：2001-08-07

申请号：US09754350

申请日：2001-01-05

申请人： Chih-Cheng Liu ,  De-Yuan Wu

发明人： Chih-Cheng Liu ,  De-Yuan Wu

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

摘要： A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (LCG) and the floating gate channel length (LFG) is 0.25 micrometers and about 3.5 nm, respectively.

摘要翻译： 公开了一种制造掩埋垂直分离栅极存储单元的方法。 首先，在用于容纳浮动栅极的SOI衬底中形成第一沟槽。 然后在第一沟槽的底部形成具有比第一沟槽小的宽度的第二沟槽，用于容纳字线/控制门。 同时，产生硅侧壁台阶结构并用作埋入垂直分离栅极存储单元的垂直沟道，其中垂直控制栅极沟道长度（LCG）和浮动栅极沟道长度（LFG）为0.25微米，约3.5nm ， 分别。

公开(公告)号：US06466474B1

公开(公告)日：2002-10-15

申请号：US09682399

申请日：2001-08-30

申请人： Chih-Cheng Liu ,  De-Yuan Wu

发明人： Chih-Cheng Liu ,  De-Yuan Wu

IPC分类号： G11C1124

CPC分类号： G11C11/24 ,  G11C11/404 ,  G11C11/405

摘要： A memory module stores digital data. The memory module has many memory cells biased by a voltage source. Each memory cell has an access transistor electrically connected to a word line and a bit line for receiving bits from the bit line when the word line turns on the access transistor, a switching circuit electrically connected to the access transistor, and a capacitor electrically connected to the switching circuit. The switching circuit turns on or off according to the bit from the access transistor. The capacitor stores charge supplied by the switching circuit when the switching circuit turns on. The capacitor stores charge supplied by the voltage source when the switching circuit turns off. When the access transistor turns off, the switching circuit or the voltage source provides charge to the capacitor to sustain the voltage level of the capacitor to compensate for charge leakage of the capacitor.

摘要翻译： 存储器模块存储数字数据。 存储器模块具有由电压源偏置的许多存储器单元。 每个存储单元具有电连接到字线的存取晶体管和用于当字线导通存取晶体管时从位线接收位的位线，电连接到存取晶体管的开关电路和电连接到 开关电路。 根据存取晶体管的位，开关电路导通或关断。 当开关电路导通时，电容器存储由开关电路提供的电荷。 当开关电路断开时，电容器存储由电压源提供的电荷。 当存取晶体管截止时，开关电路或电压源向电容器提供电荷，以维持电容器的电压电平，以补偿电容器的电荷泄漏。

公开(公告)号：US06368964B1

公开(公告)日：2002-04-09

申请号：US09731839

申请日：2000-12-08

申请人： Hsin-Hui Hsu ,  De-Yuan Wu

发明人： Hsin-Hui Hsu ,  De-Yuan Wu

IPC分类号： H01L21302

CPC分类号： H01L21/7685 ,  H01L21/31683 ,  H01L21/76886 ,  H01L21/76888

摘要： The present invention provides a method of reducing resistance in an Al-containing conductor. An Al oxide layer is first formed on the surface of an Al-containing conductor followed by the formation of a Ti layer and a barrier layer above the Al oxide layer, respectively. Finally, a W contact plug is formed within the barrier layer. The Al oxide layer functions in preventing a reaction between the Ti layer and the conductor during high temperature formation of the W contact plugs to avoid the influence of resistance in the Al-containing conductor.

摘要翻译： 本发明提供一种降低含Al导体电阻的方法。 首先在含Al导体的表面上形成Al氧化物层，然后分别在Al氧化物层上方形成Ti层和阻挡层。 最后，在阻挡层内形成W接触塞。 Al氧化物层在W接触插塞的高温形成期间用于防止Ti层和导体之间的反应，以避免含Al导体中的电阻的影响。

公开(公告)号：US06326261B1

公开(公告)日：2001-12-04

申请号：US09754345

申请日：2001-01-05

申请人： Ling-Hsu Tsang ,  De-Yuan Wu

发明人： Ling-Hsu Tsang ,  De-Yuan Wu

IPC分类号： H01L218242

CPC分类号： H01L27/10867

摘要： A method of fabricating a deep trench capacitor is achieved. A deep trench is formed in a silicon substrate followed by the formation of a buried plate in the silicon substrate beneath the deep trench. A silicon nitride layer is formed on the surface of the deep trench above the buried plate. An oxidation process is performed to simultaneously form a first oxide film on the silicon nitride layer and a second oxide film on the silicon substrate within the deep trench. A doped polysilicon layer is formed in the deep trench with its surface lowered down to the surface of the substrate. Finally, a portion of the second oxide film is removed to expose the substrate in the upper region of the deep trench followed by the filling in of an undoped polysilicon layer into the deep trench to finish the fabrication process of the DRAM deep trench capacitor.

摘要翻译： 实现了制造深沟槽电容器的方法。 在硅衬底中形成深沟槽，随后在深沟槽下方的硅衬底中形成掩埋板。 在掩埋板上方的深沟槽的表面上形成氮化硅层。 进行氧化处理以在氮化硅层上同时形成第一氧化物膜，并在深沟槽内在硅衬底上形成第二氧化物膜。 在深沟槽中形成掺杂多晶硅层，其表面向下降到衬底的表面。 最后，去除第二氧化膜的一部分以暴露深沟槽的上部区域中的衬底，然后将未掺杂的多晶硅层填充到深沟槽中，以完成DRAM深沟槽电容器的制造过程。