公开(公告)号：US06432827B1

公开(公告)日：2002-08-13

申请号：US09725027

申请日：2000-11-29

申请人： Sun-Chieh Chien ,  De-Yuan Wu ,  Yung-Chung Lin

发明人： Sun-Chieh Chien ,  De-Yuan Wu ,  Yung-Chung Lin

IPC分类号： H01L21461

CPC分类号： H01L21/31056 ,  H01L27/10897

摘要： The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

摘要翻译： 本发明提供了EDRAM的层间电介质的平面化方法。 该方法包括在EDRAM的半导体晶片上限定外围电路区域和存储器阵列区域，以及形成多个MOS晶体管和电容器。 同样，使用电容器的存储节点的布局图案作为反向掩模，在半导体晶片上形成电介质层和光致抗蚀剂层以进行蚀刻处理。 因此，存储器阵列区域中的光致抗蚀剂层的部分被去除，同时将存储器阵列区域中的介电层蚀刻预定深度。 最后，在电介质层上进行化学机械抛光工艺，以平坦化EDRAM的层间电介质。

公开(公告)号：US06509235B2

公开(公告)日：2003-01-21

申请号：US09764333

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L218232

CPC分类号： H01L27/105 ,  H01L21/82345 ,  H01L27/1052

摘要： The present invention provides a method for forming an embedded memory MOS. The method involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer. Thereafter, a protective layer is formed on the surface of the semiconductor wafer, followed by a first photolithographic and etching process (PEP) to define a plurality of gate patterns in the protective layer in the memory array area. Then, a second PEP is applied to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area to simultaneously form a gate of each MOS in the periphery circuits region and the memory array area. Finally, a lightly doped drain (LDD) of each MOS is formed, as well as a spacer and a source/drain (S/D) adjacent to each gate in the periphery circuits region.

摘要翻译： 本发明提供一种形成嵌入式存储器MOS的方法。 该方法包括首先在具有限定的存储器阵列区域和外围电路区域的半导体晶片的表面上分别形成介电层和未掺杂的多晶硅层。 然后，将存储器阵列区域中未掺杂的多晶硅层掺杂成为掺杂多晶硅层。 此后，在半导体晶片的表面上形成保护层，然后进行第一光刻和蚀刻工艺（PEP），以在存储器阵列区域中的保护层中限定多个栅极图案。 然后，施加第二PEP以蚀刻外围电路区域中的未掺杂多晶硅层和存储器阵列区域中的掺杂多晶硅层，以在外围电路区域和存储器阵列区域中同时形成每个MOS的栅极。 最后，形成每个MOS的轻掺杂漏极（LDD），以及与外围电路区域中的每个栅极相邻的间隔物和源极/漏极（S / D）。

公开(公告)号：US06465364B2

公开(公告)日：2002-10-15

申请号：US09764328

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L21/28518 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： The present invention provides a method for the formation of contact plugs of an embedded memory. The method first forms a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region, and plurality of landing pads is formed in the first dielectric layer. Next, both a stop layer and a second dielectric layer are formed, respectively, on the surface of semiconductor wafer. A PEP process is then used to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to form in-situ each contact plug in both the memory array region and the periphery circuit region.

摘要翻译： 本发明提供一种用于形成嵌入式存储器的接触塞的方法。 该方法首先在半导体晶片的限定的存储器阵列区域和外围电路区域上形成多个MOS晶体管。 然后，在存储器阵列区域上形成第一电介质层，并且在第一介电层中形成多个着陆焊盘。 接下来，在半导体晶片的表面上分别形成停止层和第二电介质层。 然后使用PEP工艺在存储器阵列区域和外围电路区域中的第二介电层中形成多个接触插塞孔。 最后，将导电层填充到每个孔中，以在存储器阵列区域和外围电路区域中的原位形成每个接触插塞。

公开(公告)号：US06406968B1

公开(公告)日：2002-06-18

申请号：US09767499

申请日：2001-01-23

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

摘要： A method of forming a dynamic random access memory. A substrate having a memory cell region and a logic circuit region is provided. The substrate also has a first dielectric layer thereon. The first dielectric layer in the memory cell region has a bit line and a node contact while the first dielectric layer in the logic circuit region has a first metallic interconnect. An intermediate dielectric layer is formed over the first dielectric layer such that the intermediate dielectric layer in the logic circuit region has a second metallic interconnect that connects electrically with the first metallic interconnect. A capacitor is formed in the intermediate dielectric layer within the memory cell region. A second dielectric layer is formed over the substrate. A third metallic interconnect is formed in the second dielectric layer such that the third metallic interconnect and the second metallic interconnect are electrically connected.

摘要翻译： 一种形成动态随机存取存储器的方法。 提供具有存储单元区域和逻辑电路区域的衬底。 衬底上也具有第一介电层。 存储单元区域中的第一介电层具有位线和节点接​​触，而逻辑电路区域中的第一介电层具有第一金属互连。 中间电介质层形成在第一电介质层上，使得逻辑电路区域中的中间介电层具有与第一金属互连电连接的第二金属互连。 在存储单元区域内的中间介质层中形成电容器。 第二介质层形成在衬底上。 在第二电介质层中形成第三金属互连，使得第三金属互连和第二金属互连电连接。

公开(公告)号：US06248623B1

公开(公告)日：2001-06-19

申请号：US09439170

申请日：1999-11-12

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L28242

CPC分类号： H01L27/10894 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

摘要： A method of manufacturing an embedded memory. A substrate has a memory cell region and a logic circuit region. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than those between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill space between the first gate structures in the memory cell region. A source/drain region is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region. A silicide layer is formed on the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.

摘要翻译： 一种制造嵌入式存储器的方法。 衬底具有存储单元区域和逻辑电路区域。 多个第一栅极结构和多个第二栅极结构分别形成在存储单元区域和逻辑电路区域中的衬底上。 第一栅极结构之间的每个空间都小于第二栅极结构之间的间隔。 在每个第一栅极结构的侧壁上并且在每个第二栅极结构的侧壁之上形成第一间隔物。 在由第一间隔物和逻辑电路区域中的第二栅极结构暴露的衬底中形成几个轻掺杂漏极区。 在逻辑电路区域中的每个第一间隔物上形成第二间隔物，同时形成硅化物块以填充存储单元区域中的第一栅极结构之间的空间。 源极/漏极区域形成在由第二间隔物暴露的衬底中，第一间隔物和第二栅极结构在逻辑电路区域中。 在由第二间隔物暴露的衬底上形成硅化物层，在逻辑电路区域中形成第一间隔物和第二栅极结构。

公开(公告)号：US6110827A

公开(公告)日：2000-08-29

申请号：US655074

申请日：1996-06-03

申请人： Sun-Chieh Chien ,  Der-Yuan Wu ,  Kun-Cho Chen

发明人： Sun-Chieh Chien ,  Der-Yuan Wu ,  Kun-Cho Chen

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76819 ,  Y10S438/959

摘要： A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.

摘要翻译： 用于自对准接触工艺的平面化方法，适用于DRAM处理。 在形成电容器的底部端子层之前，首先将衬底表面平坦化，从而在随后蚀刻限定的图案期间避免由起伏的表面轮廓引起的纵梁效应和相关的桥接问题。 此外，根据本发明的方法，首先通过覆盖首先沉积氧化物层的MOS晶体管的硅衬底，然后蚀刻鉴别层，最后是平坦化层，具有平滑的平面表面的衬底 获得。

公开(公告)号：US6107175A

公开(公告)日：2000-08-22

申请号：US27844

申请日：1998-02-23

申请人： Han Lin ,  Sun-Chieh Chien ,  Jengping Lin

发明人： Han Lin ,  Sun-Chieh Chien ,  Jengping Lin

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L21/3205

CPC分类号： H01L21/76897 ,  H01L21/28525

摘要： A method of a method of fabricating a contact. A substrate having a plurality of gates and a plurality of lightly doped source/drain regions is provided. A dielectric layer is formed and patterned to form a self-align contact window to expose a first lightly doped source/drain region of said lightly doped source/drain regions, and to form a first spacer on a side wall of a first gate of said gates simultaneously. An ion implantation is performed by using the first spacer as a mask, so that a first heavily doped source/drain region is formed in the first lightly doped source/drain region. A doped poly-silicon layer is formed over the substrate, and a metal silicide layer is formed on the doped poly-silicon layer. The doped poly-silicon and the metal silicide layer are patterned to form a self-align contact.

摘要翻译： 一种制造触点的方法的方法。 提供具有多个栅极和多个轻掺杂源极/漏极区域的衬底。 形成介电层并图案化以形成自对准接触窗口，以暴露所述轻掺杂源极/漏极区域的第一轻掺杂源极/漏极区域，并在所述第一栅极的侧壁上形成第一间隔物 同时门。 通过使用第一间隔件作为掩模来执行离子注入，使得在第一轻掺杂源极/漏极区域中形成第一重掺杂源极/漏极区域。 在衬底上形成掺杂多晶硅层，并且在掺杂多晶硅层上形成金属硅化物层。 将掺杂的多晶硅和金属硅化物层图案化以形成自对准接触。

公开(公告)号：US5874334A

公开(公告)日：1999-02-23

申请号：US8900

申请日：1998-01-20

申请人： Jason Jenq ,  Sun-Chieh Chien

发明人： Jason Jenq ,  Sun-Chieh Chien

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40

摘要： A method for fabricating a DRAM capacitor comprising the steps of forming silicon nitride spacers twice, not only serving as etching stop layer in a self-aligned contact etching process, but also used as a protective layer for the bit line and gate electrode in an etching operation. In another aspect, using silicon nitride spacers has the advantage of being capable of increasing the width of a contact opening. Hence, a contact opening having a smaller height to width ratio can be produced. Furthermore, the lower electrode of the capacitor in this invention is a pillar-shaped structure, and together with the formation of a hemispherical grained silicon layer over the lower electrode, the surface area of the capacitor can be greatly increased. Moreover, a dielectric layer having a high dielectric constant can be used; hence, a capacitor with sufficient capacitance can be provided although the surface area of the storage capacitor is reduced.

摘要翻译： 一种用于制造DRAM电容器的方法，包括以下步骤：形成氮化硅间隔物两次，不仅用作自对准接触蚀刻工艺中的蚀刻停止层，而且还用作蚀刻中的位线和栅电极的保护层 操作。 在另一方面，使用氮化硅间隔物具有能够增加接触开口的宽度的优点。 因此，可以制造具有较小高度与宽度比的接触开口。 此外，本发明的电容器的下部电极为柱状结构，并且在下部电极上形成半球状的硅层，能够大幅提高电容器的表面积。 此外，可以使用具有高介电常数的介电层; 因此，尽管存储电容器的表面积减小，但是可以提供具有足够电容的电容器。

公开(公告)号：US5624870A

公开(公告)日：1997-04-29

申请号：US405489

申请日：1995-03-16

申请人： Sun-Chieh Chien ,  Yu-Ju Liu

发明人： Sun-Chieh Chien ,  Yu-Ju Liu

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76838 ,  H01L21/7684

摘要： A method of planarizing an electrical contact region in a silicon substrate uses spin-on-glass or polysilicon as plug material (42) to fill a contact hole (34). A device or doped region (31) is formed at the surface of the substrate (30) and an insulating layer (33) is formed over the substrate so that the entire doped region is covered by the insulating layer. The contact hole is then formed through the insulating layer to expose a portion of the doped region. To increase the conductivity of the doped region through the contact hole, a filler layer of either spin-on-glass or polysilicon, thick enough to substantially fill the contact hole, is formed over the insulating layer. The filler layer is then etched away from the portions around the contact hole by a conventional dry or wet oxide etching process.

摘要翻译： 平面化硅衬底中的电接触区域的方法使用旋涂玻璃或多晶硅作为插塞材料（42）填充接触孔（34）。 在衬底（30）的表面上形成器件或掺杂区域（31），并且在衬底上形成绝缘层（33），使得整个掺杂区域被绝缘层覆盖。 然后通过绝缘层形成接触孔以暴露掺杂区域的一部分。 为了增加通过接触孔的掺杂区的导电性，在绝缘层上形成厚度足以基本上填充接触孔的旋涂玻璃或多晶硅的填充层。 然后通过常规的干或湿氧化物蚀刻工艺将填料层从接触孔周围的部分蚀刻掉。

公开(公告)号：US5521113A

公开(公告)日：1996-05-28

申请号：US405078

申请日：1995-03-16

申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien

发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien

IPC分类号： H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S148/02

摘要： An SRAM cell includes a semiconductor substrate doped with a dopant of a first type, a highly doped region in the substrate implanted with a dopant of opposite type, a gate oxide layer on the substrate, a first conductive layer formed upon the gate oxide layer, a dielectric layer deposited over the first conductive layer, an opening in the gate oxide layer, the first conductive layer, and the dielectric layer, and a second conductive layer deposited upon the dielectric layer.

摘要翻译： SRAM单元包括掺杂有第一类型的掺杂剂的半导体衬底，注入相反类型的掺杂剂的衬底中的高度掺杂区域，衬底上的栅极氧化物层，形成在栅极氧化物层上的第一导电层， 沉积在第一导电层上的电介质层，栅极氧化物层中的开口，第一导电层和介电层，以及沉积在电介质层上的第二导电层。