公开(公告)号：US6130161A

公开(公告)日：2000-10-10

申请号：US866777

申请日：1997-05-30

Applicant: Leon Ashley ,  Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore ,  Richard G. Smith

Inventor： Leon Ashley ,  Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore ,  Richard G. Smith

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with halfnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper intersititial positions.

Abstract translation: 提供具有改善的电迁移和耐腐蚀性的亚半微米铜互连的方法。 该方法包括使用电镀铜的双镶嵌，其中晶种层转变为金属间层。 提供了一种具有铌，镧，锆或锡的铜金属间化合物，以提高电迁移率和降低缺陷敏感性。 还提供了一种在铜线顶上形成帽的方法，以提高完全覆盖表面的耐腐蚀性。 还描述了结构和方法，以通过在铜中间位置引入碳原子来改善电迁移和耐腐蚀性。

公开(公告)号：US20070205515A1

公开(公告)日：2007-09-06

申请号：US11746508

申请日：2007-05-09

Applicant: Birendra AGARWALA ,  Du Binh NGUYEN ,  Hazara RATHORE

Inventor： Birendra AGARWALA ,  Du Binh NGUYEN ,  Hazara RATHORE

IPC: H01L23/52

CPC classification number: H01L21/76847 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Device with a damascene interconnect for integrated circuits with improved reliability and improved electromigration properties. The device including a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line.

Abstract translation: 具有用于集成电路的镶嵌互连的装置，具有改进的可靠性和改善的电迁移特性。 该装置包括具有金属线和通孔的双镶嵌线，以及布置成划分金属线的冗余衬垫。

公开(公告)号：US07163883B2

公开(公告)日：2007-01-16

申请号：US10694500

申请日：2003-10-27

Applicant: Birendra N. Agarwala ,  Hormazdyar Minocher Dalal ,  Eric G. Liniger ,  Diana Llera-Hurlburt ,  Du Binh Nguyen ,  Richard W. Procter ,  Hazara Singh Rathore ,  Chunyan E. Tian ,  Brett H. Engel

Inventor： Birendra N. Agarwala ,  Hormazdyar Minocher Dalal ,  Eric G. Liniger ,  Diana Llera-Hurlburt ,  Du Binh Nguyen ,  Richard W. Procter ,  Hazara Singh Rathore ,  Chunyan E. Tian ,  Brett H. Engel

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L21/76831 ,  H01L21/76801 ,  H01L21/76807

Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Abstract translation: 围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。 边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。 电介质壁是与低k层间电介质不同的材料。

公开(公告)号：US06287954B1

公开(公告)日：2001-09-11

申请号：US09457960

申请日：1999-12-09

Applicant: Leon Ashley ,  Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore ,  Richard G. Smith

Inventor： Leon Ashley ,  Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore ,  Richard G. Smith

IPC: H01L214763

CPC classification number: H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with hafnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.

Abstract translation: 提供具有改善的电迁移和耐腐蚀性的亚半微米铜互连的方法。 该方法包括使用电镀铜的双镶嵌，其中晶种层转变为金属间层。 提供了一种具有铪，镧，锆或锡的铜金属间化合物，以提高电迁移率和降低缺陷敏感性。 还提供了一种在铜线顶上形成帽的方法，以提高完全覆盖表面的耐腐蚀性。 还描述了结构和方法，以通过将碳原子并入铜间隙位置来改善电迁移和耐腐蚀性。

公开(公告)号：US5981374A

公开(公告)日：1999-11-09

申请号：US841221

申请日：1997-04-29

Applicant: Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore

Inventor： Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L21/441

CPC classification number: H01L21/76807 ,  H01L21/76802

Abstract: The present invention relates to the field of semiconductor manufacturing, and more specifically to methods of forming sub-half-micron multi-level interconnect structures for integrated circuits. The inventive structure and process are spike free and that has resulted in improved circuit performance, reliability and process yields. The inventive structure and process have a plurality of insulator layers where each of the adjoining insulator layers are of a different material.

Abstract translation: 本发明涉及半导体制造领域，更具体地涉及形成用于集成电路的次半微米多级互连结构的方法。 本发明的结构和工艺是无尖峰的，并且导致改进的电路性能，可靠性和工艺产量。 本发明的结构和工艺具有多个绝缘体层，其中每个相邻的绝缘体层是不同的材料。

公开(公告)号：US06294835B1

公开(公告)日：2001-09-25

申请号：US09365684

申请日：1999-08-02

Applicant: Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore

Inventor： Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore

IPC: H01L2348

CPC classification number: H01L23/5226 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.

Abstract translation: 本发明一般涉及新的顺序的方法和材料，以通过明智地使用复合绝缘体来防止金属通过插塞硬化金属稀化，从而提高工艺产量并提高具有亚半微米几何尺寸的多层互连的可靠性，以及 通过防止工艺诱发的金属尖峰形成。 该方法利用双镶嵌工艺。 在这种方法中通过使用一对需要不同化学蚀刻的绝缘体来防止金属尖峰和由过度蚀刻工艺引起的金属变薄。

公开(公告)号：US20070111497A1

公开(公告)日：2007-05-17

申请号：US11164223

申请日：2005-11-15

Applicant: Birendra Agarwala ,  Du Binh Nguyen ,  Hazara Rathore

Inventor： Birendra Agarwala ,  Du Binh Nguyen ,  Hazara Rathore

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76847 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.

Abstract translation: 装置及其制造方法。 该装置包括具有金属线和通孔的双镶嵌线，以及布置成划分金属线的冗余衬垫。 该方法包括在双镶嵌线的金属条中形成沟槽，在沟槽中沉积阻挡层，并用金属填充沟槽的其余部分。

公开(公告)号：US06348731B1

公开(公告)日：2002-02-19

申请号：US09240950

申请日：1999-01-29

Applicant: Leon Ashley ,  Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore ,  Richard G. Smith

Inventor： Leon Ashley ,  Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore ,  Richard G. Smith

IPC: H01L2348

CPC classification number: H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with hafnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.

Abstract translation: 提供具有改进的电迁移和耐腐蚀性的亚半微米铜互连的方法。该方法包括使用电镀铜的双镶嵌，其中种子层转变为金属间层。 提供了一种具有铪，镧，锆或锡的铜金属间化合物，以提高电迁移率和降低缺陷敏感性。还提供了一种在铜线上形成帽以提高耐腐蚀性的方法，其完全覆盖表面 还描述了结构和方法，以通过将碳原子并入铜间隙位置来改善电迁移和耐腐蚀性。

公开(公告)号：US6133139A

公开(公告)日：2000-10-17

申请号：US947244

申请日：1997-10-08

Applicant: Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore

Inventor： Hormazdyar M. Dalal ,  Du Binh Nguyen ,  Hazara S. Rathore

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/52

CPC classification number: H01L23/5226 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/485 ,  H01L2924/0002

Abstract: The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.

Abstract translation: 本发明一般涉及新的顺序的方法和材料，以通过明智地使用复合绝缘体来防止金属通过插塞硬化金属稀化，从而提高工艺产量并提高具有亚半微米几何尺寸的多层互连的可靠性，以及 通过防止工艺诱发的金属尖峰形成。 该方法利用双镶嵌工艺。 在这种方法中通过使用一对需要不同化学蚀刻的绝缘体来防止金属尖峰和由过度蚀刻工艺引起的金属变薄。

公开(公告)号：US07279411B2

公开(公告)日：2007-10-09

申请号：US11164223

申请日：2005-11-15

Applicant: Birendra N. Agarwala ,  Du Binh Nguyen ,  Hazara Singh Rathore

Inventor： Birendra N. Agarwala ,  Du Binh Nguyen ,  Hazara Singh Rathore

IPC: H01L21/4763

CPC classification number: H01L21/76847 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.

Abstract translation: 装置及其制造方法。 该装置包括具有金属线和通孔的双镶嵌线，以及布置成划分金属线的冗余衬垫。 该方法包括在双镶嵌线的金属条中形成沟槽，在沟槽中沉积阻挡层，并用金属填充沟槽的其余部分。