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1.发明授权公开(公告)号：US09018089B2
公开(公告)日：2015-04-28
申请号：US13221698
申请日：2011-08-30
申请人： Eric G. Liniger , Griselda Bonilla , Pak Leung , Stephen A. Cohen , Stephen M. Gates , Thomas M. Shaw
发明人： Eric G. Liniger , Griselda Bonilla , Pak Leung , Stephen A. Cohen , Stephen M. Gates , Thomas M. Shaw
IPC分类号： H01L21/26 , H01L21/3105 , H01L21/66 , H01L21/768
CPC分类号： H01L21/3105 , H01L21/76828 , H01L21/76829 , H01L22/14
摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。
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2.发明授权Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties 失效低k电介质CVD膜形成过程与原位嵌入的纳米层以改善机械性能公开(公告)号：US07998880B2
公开(公告)日：2011-08-16
申请号：US11830425
申请日：2007-07-30
IPC分类号： H01L21/76
CPC分类号： H01L21/76801 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02354 , H01L21/3105 , H01L21/31633 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.
摘要翻译： 具有约3.0或更小的有效介电常数k的低k电介质堆叠，其中通过将至少一个纳米层引入电介质叠层来提高堆叠的机械性能。 在不显着增加叠层内的膜的介电常数并且不需要使本发明的电介质叠层进行任何后处理步骤的情况下，实现机械性能的改善。 具体地，本发明提供了一种低k电介质堆叠，其包含至少一个低k电介质材料和存在于至少一个低k电介质材料内的至少一个纳米层。
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公开(公告)号：US07678673B2
公开(公告)日：2010-03-16
申请号：US11832368
申请日：2007-08-01
申请人： Elbert Huang , William F. Landers , Michael Lane , Eric G. Liniger , Xiao H. Liu , David L. Questad , Thomas M. Shaw
发明人： Elbert Huang , William F. Landers , Michael Lane , Eric G. Liniger , Xiao H. Liu , David L. Questad , Thomas M. Shaw
CPC分类号： H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.
摘要翻译： 本发明提供了一种加强结构的方法，以治愈结构的缺陷，加强结构，从而加强电介质，而不影响结构的理想的低介电常数。 本发明的方法包括提供具有至少一个互连结构的半导体结构的步骤; 切割互连结构; 将至少一个渗透剂施加到所述互连结构中; 并渗透渗透剂渗透到互连结构中。
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公开(公告)号：US07573130B1
公开(公告)日：2009-08-11
申请号：US12357721
申请日：2009-01-22
申请人： Thomas M Shaw , Michael W Lane , Xio Hu Liu , Griselda Bonilla , James P Doyle , Howard S Landis , Eric G Liniger
发明人： Thomas M Shaw , Michael W Lane , Xio Hu Liu , Griselda Bonilla , James P Doyle , Howard S Landis , Eric G Liniger
IPC分类号： H01L23/44
CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a process for preparing a robust crack-absorbing integrated circuit chip comprising a crack trapping structure containing two metal plates and a via-bar structure sandwiched between said plates.
摘要翻译： 本发明涉及一种制备坚固的抗剥离集成电路芯片的方法，该芯片包括一个包含两个金属板的裂纹捕获结构和夹在所述板之间的通孔杆结构。
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公开(公告)号：US20090035480A1
公开(公告)日：2009-02-05
申请号：US11832368
申请日：2007-08-01
申请人： Elbert Huang , William F. Landers , Michael Lane , Eric G. Liniger , Xiao H. Liu , David L. Questad , Thomas M. Shaw
发明人： Elbert Huang , William F. Landers , Michael Lane , Eric G. Liniger , Xiao H. Liu , David L. Questad , Thomas M. Shaw
CPC分类号： H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.
摘要翻译： 本发明提供了一种加强结构的方法，以治愈结构的缺陷，加强结构，从而加强电介质，而不影响结构的理想的低介电常数。 本发明的方法包括提供具有至少一个互连结构的半导体结构的步骤; 切割互连结构; 将至少一个渗透剂施加到所述互连结构中; 并渗透渗透剂渗透到互连结构中。
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公开(公告)号：US07163883B2
公开(公告)日：2007-01-16
申请号：US10694500
申请日：2003-10-27
申请人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
发明人： Birendra N. Agarwala , Hormazdyar Minocher Dalal , Eric G. Liniger , Diana Llera-Hurlburt , Du Binh Nguyen , Richard W. Procter , Hazara Singh Rathore , Chunyan E. Tian , Brett H. Engel
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/8238
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76807
摘要： An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
摘要翻译： 围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。 边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。 电介质壁是与低k层间电介质不同的材料。
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7.发明申请公开(公告)号：US20130049207A1
公开(公告)日：2013-02-28
申请号：US13221698
申请日：2011-08-30
申请人： Eric G. Liniger , Griselda Bonilla , Pak Leung , Stephan A. Cohen , Stephen M. Gates , Thomas M. Shaw
发明人： Eric G. Liniger , Griselda Bonilla , Pak Leung , Stephan A. Cohen , Stephen M. Gates , Thomas M. Shaw
IPC分类号： H01L21/26 , H01L23/485 , H01L21/66
CPC分类号： H01L21/3105 , H01L21/76828 , H01L21/76829 , H01L22/14
摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。
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8.发明授权Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification 失效通过表面改性来提高半导体器件的温度/湿度/偏置性能的方法和结构公开(公告)号：US07517790B2
公开(公告)日：2009-04-14
申请号：US10906189
申请日：2005-02-08
IPC分类号： H01L21/44
CPC分类号： H01L23/564 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method is disclosed of repairing wire bond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-K dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.
摘要翻译： 公开了一种修复诸如高速半导体微处理器，专用集成电路（ASIC）和其它高速集成电路器件的半导体芯片上的引线键合损伤的方法，特别是使用低K电介质材料的器件。 该方法涉及使用反应性液体的表面改性。 在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗 湿度进入，从而提高这种半导体器件的温度/湿度/偏差（THB）性能。
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公开(公告)号：US07491578B1
公开(公告)日：2009-02-17
申请号：US12060937
申请日：2008-04-02
申请人： Thomas M Shaw , Michael W Lane , Xio Hu Liu , Griselda Bonilla , James P Doyle , Howard S Landis , Eric G Liniger
发明人： Thomas M Shaw , Michael W Lane , Xio Hu Liu , Griselda Bonilla , James P Doyle , Howard S Landis , Eric G Liniger
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a process for preparing a robust crack-absorbing integrated circuit chip comprising a crack trapping structure containing two metal plates and a via-bar structure sandwiched between said plates.
摘要翻译： 本发明涉及一种制备坚固的抗剥离集成电路芯片的方法，该芯片包括一个包含两个金属板的裂纹捕获结构和夹在所述板之间的通孔杆结构。
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10.发明授权Method and system for dicing wafers, and semiconductor structures incorporating the products thereof 失效用于切割晶片的方法和系统，以及结合其产品的半导体结构公开(公告)号：US06915795B2
公开(公告)日：2005-07-12
申请号：US10448305
申请日：2003-05-30
申请人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
发明人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
IPC分类号： B23D59/00 , B28D5/02 , H01L21/301 , H01L21/607 , H01L21/78 , H01L29/06 , B28D1/04
CPC分类号： H01L24/85 , B23D59/002 , B28D5/022 , H01L21/78 , H01L24/48 , H01L29/0657 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/78302 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , Y10T83/0259 , Y10T83/0378 , Y10T83/0581 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.
摘要翻译： 一种用于切割半导体晶片的方法和系统，其提供具有大大减小的背面切屑和开裂的结构，以及增加的模具强度。 还包括从根据本发明切割的晶片获得的半导体芯片结构。
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