公开(公告)号：US07470949B1

公开(公告)日：2008-12-30

申请号：US11828213

申请日：2007-07-25

申请人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

发明人： Bomy Chen ,  Yuniarto Widjaja ,  Jack Edward Frayer ,  Felix (Ying-Kit) Tsui

IPC分类号： H01L27/108

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

摘要： A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.

摘要翻译： 非易失性存储单元具有用于在其上存储电荷的电荷捕获层。 电池是第一导电性衬底中的双向电池。 电池具有两个间隔开的沟槽。 在每个沟槽内，其底部是第二导电性的区域。 一个通道从一个沟槽底部的一个区域沿着该沟槽的侧壁延伸到衬底的顶部平坦表面，并且沿相邻沟槽的侧壁延伸到相邻沟槽底部的区域 。 捕获层沿着两个沟槽中的每一个的侧壁。 控制栅极位于每个沟槽中，每个沟槽沿着侧壁电容耦合到捕获层，并且在沟槽的底部与区域电容耦合。 每个沟槽可以存储多个位。

公开(公告)号：US07358559B2

公开(公告)日：2008-04-15

申请号：US11239791

申请日：2005-09-29

申请人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

发明人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.

摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。 相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。 相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

公开(公告)号：US07403418B2

公开(公告)日：2008-07-22

申请号：US11241582

申请日：2005-09-30

申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

公开(公告)号：US06756632B1

公开(公告)日：2004-06-29

申请号：US10641609

申请日：2003-08-15

申请人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

发明人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

IPC分类号： H01L29788

CPC分类号： H03K19/17748 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/7885 ,  H03K19/1778

摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a floating gate positioned over a first portion of the channel and a control gate positioned over a second portion of the channel with electrons being injected onto the floating gate by hot electron injection mechanism. The nonvolatile memory cell is erased by the action of the electrons from the floating gate being tunneled through Fowler-Nordheim tunneling onto the control gate, which is adjacent to the second region. As a result, no high voltage is ever applied to the second region during program or erase. Thus, the nonvolatile memory cell with the second region can be connected directly to the gate of the MOS transistor, which together therewith forms a nonvolatile reprogrammable switch.

摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有位于通道的第一部分上方的浮动栅极的分离栅极型，以及位于通道的第二部分上方的控制栅极，其中电子通过热电子注入机制注入浮置栅极。 非易失性存储单元被来自浮动栅极的电子的作用擦除，通过Fowler-Nordheim隧穿隧道穿过与第二区域相邻的控制栅极。 因此，在编程或擦除期间，不会对第二区域施加高电压。 因此，具有第二区域的非易失性存储单元可以直接连接到MOS晶体管的栅极，其一起形成非易失性可编程开关。

公开(公告)号：US07800159B2

公开(公告)日：2010-09-21

申请号：US11923515

申请日：2007-10-24

申请人： Yuniarto Widjaja ,  Henry A. O'M'Mani ,  Prateep Tuntasood ,  Bomy Chen

发明人： Yuniarto Widjaja ,  Henry A. O'M'Mani ,  Prateep Tuntasood ,  Bomy Chen

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, and a second region of the second conductivity, spaced apart from the first region, with a channel region therebetween. The channel region has a first portion adjacent to the first region, a third portion adjacent to the second region and a second portion therebetween. A first and second floating gates are over the first portion and third portion respectively and are insulated therefrom. A first and second control gates are over the first and second floating gates respectively and are capacitively coupled thereto. A first and second erase gates are over the first and second regions respectively and are insulated therefrom. A word line is over the second portion and is insulated therefrom. Electrical contacts to the array are made along the extremities of the array.

摘要翻译： 多个非易失性存储单元单元以第一导电类型的单晶半导体衬底中的行和列布置。 每个单元单元具有沿着平面的基板中的第二导电类型的第一区域和与第一区域间隔开的第二导电体的第二区域，其间具有沟道区域。 通道区域具有与第一区域相邻的第一部分，与第二区域相邻的第三部分和在其间的第二部分。 第一和第二浮动栅极分别在第一部分和第三部分之上，并与之绝缘。 第一和第二控制栅极分别在第一和第二浮置栅极之上并与其电容耦合。 第一和第二擦除栅极分别在第一和第二区域之上并与之绝缘。 字线在第二部分之上并与之绝缘。 阵列的电触点沿着阵列的末端进行。

公开(公告)号：US07439572B2

公开(公告)日：2008-10-21

申请号：US11303567

申请日：2005-12-15

申请人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

发明人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。

公开(公告)号：US07242050B2

公开(公告)日：2007-07-10

申请号：US10714243

申请日：2003-11-13

申请人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

发明人： Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack Edward Frayer

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

摘要翻译： 堆叠式非易失性存储器浮栅器件具有控制栅极。 通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。 擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。 最后，为了增加密度，可以在沟槽中制造每个单元。

公开(公告)号：US07701248B2

公开(公告)日：2010-04-20

申请号：US12100406

申请日：2008-04-10

申请人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

发明人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

IPC分类号： G06F7/38 ,  H03K19/173 ,  G11C7/00

CPC分类号： H03K17/693 ,  G11C16/0433 ,  G11C16/26

摘要： The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node. Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A demultiplexer has an input, a switched input and two outputs. The output node is connected to the input of the demultiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

摘要翻译： 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。 第一和第二非易失性存储单元中的每一个用于存储与另一个相反的状态。 解复用器具有输入，开关输入和两个输出。 输出节点连接到解复用器的输入端。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。

公开(公告)号：US07351613B2

公开(公告)日：2008-04-01

申请号：US10983314

申请日：2004-11-04

申请人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

发明人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

IPC分类号： H01L21/82

CPC分类号： H01L28/20 ,  H01C17/267 ,  H01L22/22

摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).

摘要翻译： 使用电阻反馈来减少半导体电阻元件的体积的方法。 在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。 通过减小导电材料的体积，其电阻增加。 一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。 所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

公开(公告)号：US20070007581A1

公开(公告)日：2007-01-11

申请号：US11520993

申请日：2006-09-14

申请人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

发明人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

摘要翻译： 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。 一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。