公开(公告)号：US08848428B2

公开(公告)日：2014-09-30

申请号：US13548421

申请日：2012-07-13

申请人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

发明人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： G11C11/24 ,  H01L27/108 ,  G11C7/00 ,  G11C29/00 ,  H01L29/24

CPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4097

摘要： One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.

摘要翻译： 一个实施例涉及一种包括多个存储单元的存储器件，该多个存储器单元被拼凑在一起以形成存储器阵列。 存储单元包括多个存储单元，其包括设置在半导体衬底上的各自的电容器和相应的晶体管。 电容器包括设置在半导体衬底中的导电区域中的相应的下板。 字线在导电区域上延伸，并且接触将字线连接到导电区域，以将字线耦合到相应电容器的下板。 相应的晶体管被​​布置成使得晶体管的连续栅极被布置在字线的交替侧上。

公开(公告)号：US20140016399A1

公开(公告)日：2014-01-16

申请号：US13548421

申请日：2012-07-13

申请人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

发明人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： G11C11/24

CPC分类号： G11C8/14 ,  G11C11/408 ,  G11C11/4097

摘要： One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.

摘要翻译： 一个实施例涉及一种包括多个存储单元的存储器件，该多个存储器单元被拼凑在一起以形成存储器阵列。 存储单元包括多个存储单元，其包括设置在半导体衬底上的各自的电容器和相应的晶体管。 电容器包括设置在半导体衬底中的导电区域中的相应的下板。 字线在导电区域上延伸，并且接触将字线连接到导电区域，以将字线耦合到相应电容器的下板。 相应的晶体管被​​布置成使得晶体管的连续栅极被布置在字线的交替侧上。

公开(公告)号：US08638589B2

公开(公告)日：2014-01-28

申请号：US13366370

申请日：2012-02-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C16/04 ,  H01L29/788 ,  H01L29/66 ,  H01L23/52

CPC分类号： H01L21/28282 ,  G11C16/10 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.

摘要翻译： 提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。 存储单元的操作方法包括以下步骤。 在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。 编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是 设置在第二栅极和阱区域之间。

公开(公告)号：US08390056B2

公开(公告)日：2013-03-05

申请号：US13253083

申请日：2011-10-05

申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

公开(公告)号：US20120273860A1

公开(公告)日：2012-11-01

申请号：US13541755

申请日：2012-07-04

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： H01L27/06

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

公开(公告)号：US20110024823A1

公开(公告)日：2011-02-03

申请号：US12633780

申请日：2009-12-08

申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

公开(公告)号：US08363475B2

公开(公告)日：2013-01-29

申请号：US12750650

申请日：2010-03-30

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.

摘要翻译： 非易失性存储单元包括第一晶体管对以及第一和第二控制栅极。 第一晶体管对包括串联和相同类型的第一和第二晶体管。 第一和第二晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极。 第一控制栅极通过隧道结耦合到第一浮动多晶硅栅极，并且第二控制栅极通过另一隧道结耦合到第二浮动多晶硅栅极。

公开(公告)号：US20120134205A1

公开(公告)日：2012-05-31

申请号：US13366370

申请日：2012-02-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L21/28282 ,  G11C16/10 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.

摘要翻译： 提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。 存储单元的操作方法包括以下步骤。 在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。 编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是 设置在第二栅极和阱区域之间。

公开(公告)号：US20120018794A1

公开(公告)日：2012-01-26

申请号：US13253083

申请日：2011-10-05

申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

公开(公告)号：US20110242893A1

公开(公告)日：2011-10-06

申请号：US12750650

申请日：2010-03-30

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.

摘要翻译： 非易失性存储单元包括第一晶体管对以及第一和第二控制栅极。 第一晶体管对包括串联和相同类型的第一和第二晶体管。 第一和第二晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极。 第一控制栅极通过隧道结耦合到第一浮动多晶硅栅极，并且第二控制栅极通过另一隧道结耦合到第二浮动多晶硅栅极。