公开(公告)号：US20130240984A1

公开(公告)日：2013-09-19

申请号：US13420248

申请日：2012-03-14

Applicant: Chih-Chang CHENG ,  Fu-Yu CHU ,  Ruey-Hsin LIU

Inventor： Chih-Chang CHENG ,  Fu-Yu CHU ,  Ruey-Hsin LIU

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC classification number: H01L29/7809 ,  H01L21/265 ,  H01L21/2815 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 μm.

Abstract translation: 一种制造方法包括掺杂层，掺杂层上的体结构，在掺杂层中限定的沟槽，部分地填充沟槽的绝缘体，以及掩埋在掺杂层和体结构中并与掺杂层和体结构分离的第一导电特征， 绝缘体。 掺杂层具有第一类掺杂。 身体结构具有上表面并且包括身体区域。 体区具有不同于第一类掺杂的第二类型掺杂。 沟槽有一个底面。 第一导电特征从基本上与主体结构的上表面平齐的位置延伸到沟槽的底表面。 第一导电特征与掺杂层重叠重叠距离，重叠距离范围为0至2μm。

公开(公告)号：US20130134512A1

公开(公告)日：2013-05-30

申请号：US13348463

申请日：2012-01-11

Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66659

Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate

Abstract translation: 功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。 栅极电介质和栅电极设置在半导体区域上。 与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。 电介质层具有在漂移区的顶表面上方并与其接触的部分。 导电场板在电介质层的上方。 源极区域和漏极区域在栅电极的相对侧上。 漏极区域与第一漂移区域接触。 底部金属层在场板上

公开(公告)号：US09391159B2

公开(公告)日：2016-07-12

申请号：US13438600

申请日：2012-04-03

Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/861 ,  H02M3/156

CPC classification number: H01L29/6625 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0607 ,  H01L29/0653 ,  H01L29/66136 ,  H01L29/735 ,  H01L29/861 ,  H02M3/156

Abstract: A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well.

Abstract translation: 一种三阱隔离二极管，其包括具有第一导电类型的衬底和形成在衬底中的掩埋层，其中掩埋层具有第二导电类型。 三阱隔离二极管包括在衬底上形成的外延层和掩埋层，其中外延层具有第一导电类型。 三阱隔离二极管包括在外延层中形成的第一阱，其中第一阱具有第二导电类型，第二阱形成在外延层中，其中第二阱具有第一导电类型并且围绕第一阱 ，形成在外延层中的第三阱，其中第三阱具有第二导电类型并且围绕第二阱。 三阱隔离二极管包括在外延层中形成的深阱，其中深阱具有第一导电类型并且在第一阱下方延伸。

公开(公告)号：US08664718B2

公开(公告)日：2014-03-04

申请号：US13348463

申请日：2012-01-11

Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC: H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66659

Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate.

Abstract translation: 功率MOSFET包括从半导体衬底的顶表面延伸到半导体衬底中的半导体区域，其中半导体区域是第一导电类型。 栅极电介质和栅电极设置在半导体区域上。 与第一导电类型相反的第二导电类型的漂移区域从半导体衬底的顶表面延伸到半导体衬底中。 电介质层具有在漂移区的顶表面上方并与其接触的部分。 导电场板在电介质层的上方。 源极区域和漏极区域在栅电极的相对侧上。 漏极区域与第一漂移区域接触。 底部金属层在场板上。

公开(公告)号：US08796760B2

公开(公告)日：2014-08-05

申请号：US13420248

申请日：2012-03-14

Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7809 ,  H01L21/265 ,  H01L21/2815 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 μm.

Abstract translation: 一种制造方法包括掺杂层，掺杂层上的体结构，在掺杂层中限定的沟槽，部分地填充沟槽的绝缘体，以及掩埋在掺杂层和体结构中并与掺杂层和体结构分离的第一导电特征， 绝缘体。 掺杂层具有第一类掺杂。 身体结构具有上表面并且包括身体区域。 体区具有不同于第一类掺杂的第二类型掺杂。 沟槽有一个底面。 第一导电特征从基本上与主体结构的上表面平齐的位置延伸到沟槽的底表面。 第一导电特征与掺杂层重叠重叠距离，重叠距离范围为0至2μm。

公开(公告)号：US20130256833A1

公开(公告)日：2013-10-03

申请号：US13438600

申请日：2012-04-03

Applicant: Chih-Chang CHENG ,  Fu-Yu CHU ,  Ruey-Hsin LIU

Inventor： Chih-Chang CHENG ,  Fu-Yu CHU ,  Ruey-Hsin LIU

IPC: H01L27/04 ,  H01L21/02 ,  H01L29/02

CPC classification number: H01L29/6625 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0607 ,  H01L29/0653 ,  H01L29/66136 ,  H01L29/735 ,  H01L29/861 ,  H02M3/156

Abstract: A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well.

Abstract translation: 一种三阱隔离二极管，其包括具有第一导电类型的衬底和形成在衬底中的掩埋层，其中掩埋层具有第二导电类型。 三阱隔离二极管包括在衬底上形成的外延层和掩埋层，其中外延层具有第一导电类型。 三阱隔离二极管包括在外延层中形成的第一阱，其中第一阱具有第二导电类型，第二阱形成在外延层中，其中第二阱具有第一导电类型并且围绕第一阱 ，形成在外延层中的第三阱，其中第三阱具有第二导电类型并且围绕第二阱。 三阱隔离二极管包括在外延层中形成的深阱，其中深阱具有第一导电类型并且在第一阱下方延伸。