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公开(公告)号：US11641789B2
公开(公告)日：2023-05-02
申请号：US17355260
申请日：2021-06-23
发明人： Yi Jiang , Benfu Lin , Lup San Leong , Curtis Chun-I Hsieh , Wanbing Yi , Juan Boon Tan
摘要： According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.
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公开(公告)号：US11641739B2
公开(公告)日：2023-05-02
申请号：US16889726
申请日：2020-06-01
发明人： Yongshun Sun , Eng Huat Toh , Shyue Seng Tan , Xinshu Cai , Lanxiang Wang
IPC分类号： H01L27/11558 , H01L27/11539 , H01L29/66
摘要： A memory device is provided. The memory device includes an active region in a substrate, an electrically-isolated electrode, and a dielectric layer. The electrically-isolated electrode is disposed over the active region. The dielectric layer is disposed between the electrically-isolated electrode and the active region and has a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.
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公开(公告)号：US20230129914A1
公开(公告)日：2023-04-27
申请号：US17509611
申请日：2021-10-25
发明人： Xinshu Cai , Shyue Seng Tan , Vibhor Jain , John J. Pekarik , Kien Seen Daniel Chong , Yung Fu Chong , Judson R. Holt , Qizhi Liu , Kenneth J. Stein
IPC分类号： H01L29/737 , H01L29/10 , H01L29/45 , H01L29/66
摘要： The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.
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公开(公告)号：US20230121127A1
公开(公告)日：2023-04-20
申请号：US17501270
申请日：2021-10-14
IPC分类号： H01L27/02 , H01L29/735 , H01L29/08 , H02H9/04
摘要： The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.
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公开(公告)号：US11631470B2
公开(公告)日：2023-04-18
申请号：US17389397
申请日：2021-07-30
发明人： Szu Huat Goh , Shaalini Sivaramakrishnan , Li Song , Wei Fong Soh
IPC分类号： G11C29/12 , G11C5/14 , G11C11/412 , G11C29/50
摘要： A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.
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公开(公告)号：US11610837B2
公开(公告)日：2023-03-21
申请号：US17027661
申请日：2020-09-21
发明人： Xuesong Rao , Benfu Lin , Bo Li , Chengang Feng , Yudi Setiawan , Yun Ling Tan
IPC分类号： H01L23/522 , H01L23/532 , H01L21/768
摘要： A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.
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公开(公告)号：US20230085420A1
公开(公告)日：2023-03-16
申请号：US17471190
申请日：2021-09-10
IPC分类号： H01L27/02 , H01L27/06 , H01L21/8224 , H01L21/762
摘要： A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.
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公开(公告)号：US20230071580A1
公开(公告)日：2023-03-09
申请号：US17467966
申请日：2021-09-07
发明人： Curtis Chun-I Hsieh , Juan Boon Tan , Calvin Lee
IPC分类号： H01L45/00
摘要： Structures for a resistive memory element and methods of forming a structure for a resistive memory element. A resistive memory element has a first electrode, a second electrode partially embedded in the first electrode, a third electrode, and a switching layer positioned between the first electrode and the third electrode. The second electrode includes a tip positioned in the first electrode adjacent to the switching layer and a sidewall that tapers to the tip.
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公开(公告)号：US11585703B2
公开(公告)日：2023-02-21
申请号：US16700358
申请日：2019-12-02
发明人： Bin Liu , Eng-Huat Toh , Shyue Seng Tan , Kiok Boone Elgin Quek
IPC分类号： G01K7/01 , G11C11/406 , G11C11/4072 , G11C7/04
摘要： Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.
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公开(公告)号：US20230039286A1
公开(公告)日：2023-02-09
申请号：US17394723
申请日：2021-08-05
IPC分类号： H01L27/02
摘要： The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.
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