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31 条记录 (耗时 0.019 秒)

    Memory structures and methods of forming memory structures
    1.
    发明授权
    Memory structures and methods of forming memory structures 有权

    公开(公告)号：US11380703B2

    公开(公告)日：2022-07-05

    申请号：US17087683

    申请日：2020-11-03

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Xinshu Cai ,  Yongshun Sun ,  Lanxiang Wang ,  Eng Huat Toh ,  Shyue Seng Tan

    IPC分类号： H01L27/1156 ,  H01L29/06

    摘要： A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region.

    Transistor device, memory arrays, and methods of forming the same
    6.
    发明授权
    Transistor device, memory arrays, and methods of forming the same 有权

    公开(公告)号：US11164881B2

    公开(公告)日：2021-11-02

    申请号：US16127262

    申请日：2018-09-11

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Xinshu Cai ,  Shyue Seng Tan ,  Danny Pak-Chum Shum

    IPC分类号： H01L27/11524 ,  H01L29/788 ,  G11C11/56 ,  G11C16/04

    摘要： In a non-limiting embodiment, a memory array is provided having a transistor device. The transistor device includes transistor device first, second and third doped regions in a substrate. The transistor device further includes a first transistor device select gate over a region between the transistor device first doped region and the transistor device second doped region, and a second transistor device select gate over a region between the transistor device first doped region and the transistor device third doped region. The transistor device further includes a transistor device dielectric barrier extending between the first transistor device select gate and the second transistor device select gate. A width of the dielectric barrier compared to a width of the first transistor device select gate and/or the second transistor device select gate may have a ratio ranging from 0.33:1 to 5:1.

    Partially silicided nonvolatile memory devices and integration schemes
    10.
    发明授权
    Partially silicided nonvolatile memory devices and integration schemes 有权

    公开(公告)号：US11450677B2

    公开(公告)日：2022-09-20

    申请号：US17093602

    申请日：2020-11-09

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Lanxiang Wang ,  Shyue Seng Tan ,  Xinshu Cai ,  Eng Huat Toh ,  Yongshun Sun

    IPC分类号： H01L27/11521 ,  H01L27/11558 ,  H01L27/11519

    摘要： A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.