公开(公告)号：US20190238062A1

公开(公告)日：2019-08-01

申请号：US16251696

申请日：2019-01-18

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI

IPC: H02M7/487 ,  H02M7/537 ,  H03K17/0412 ,  H03K17/12 ,  H03K17/284 ,  H03K17/60 ,  H03K17/687 ,  H01L29/739

Abstract: A 3-level T-type neutral point clamped (NPC) inverter/rectifier is disclosed in which neutral point clamping is dynamically enabled/disabled responsive to load, e.g. enabled at low load for operation in a first mode as a 3-level inverter/rectifier and disabled at high/peak load for operation in a second mode as a 2-level inverter/rectifier. When the neutral clamping leg is enabled only under low load and low current, middle switches S2 and S3 can be smaller, lower cost devices with a lower current rating. Si, SiC, GaN and hybrid implementations provide options to optimize efficiency for specific load ratios and applications. For reduced switching losses and enhanced performance of inverters based on Si-IGBT power switches, a hybrid implementation of the dual-mode T-type NPC inverter is proposed, wherein switches S1 and S4 comprise Si-IGBTs and switches S2 and S3 of the neutral clamping leg comprise GaN HEMTs. Applications include electric vehicle traction inverters.

公开(公告)号：US20190140630A1

公开(公告)日：2019-05-09

申请号：US15807021

申请日：2017-11-08

Applicant: GaN Systems Inc.

Inventor： Di CHEN ,  Larry SPAZIANI

IPC: H03K17/081 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

Abstract: A GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which provides a drain voltage sense signal VDSEN. The integrated drain voltage sense circuit comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which form a resistive divider for sensing the drain voltage of SW_MAIN, and generating the drain sense voltage output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets to VDSEN=0. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate SW_MAIN by the gate driver.

公开(公告)号：US20230370059A1

公开(公告)日：2023-11-16

申请号：US17741813

申请日：2022-05-11

Applicant: GaN Systems Inc.

Inventor： Di CHEN

IPC: H03K17/22 ,  H02M1/36 ,  H02H3/24 ,  H03K17/0814 ,  H03K17/687

CPC classification number: H03K17/223 ,  H02H3/243 ,  H02M1/36 ,  H03K17/08142 ,  H03K17/687

Abstract: A protected direct-drive depletion-mode (D-mode) GaN semiconductor half-bridge power module is disclosed. Applications include high power inverter applications, such as 100kW to 200kW electric vehicle traction inverters, and other motor drives. The high-side switch is a normally-on D-mode GaN semiconductor power switch Q1 in series with a normally-off LV Si MOSFET power switch M1 and the low-side switch is a normally on D-mode GaN semiconductor power switch Q2. The gates of both Q1 and Q2 are directly driven. M1 in series with Q1 provides a high-side switch which is a normally-off device for start-up and fail-safe protection. M1 may also be used for current sensing and overcurrent protection. For example, a control circuit determines an operational mode of M1 responsive to a UVLO signal and a voltage sense signal indicative of an overcurrent event. Examples of single phase and three-phase half-bridge modules and driver circuits are described.

公开(公告)号：US20240213127A1

公开(公告)日：2024-06-27

申请号：US18522911

申请日：2023-11-29

Applicant: GAN SYSTEMS INC.

Inventor： Abhinandan DIXIT ,  An-Sheng CHENG ,  Di CHEN ,  Hossein MOUSAVIAN

IPC: H01L23/495 ,  H01L21/8234 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L21/823475 ,  H01L23/49568 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16056 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1033 ,  H01L2924/13064

Abstract: A laminated embedded die package for a power semiconductor device, wherein a laminated body comprises a layup of a plurality of electrically conductive layers and dielectric layers. The die may be mounted in thermal contact with a leadframe. Electrical connections between contact areas of the die, external contact pads of the package and internal conductive layers are made by electrically conductive vias or microvias, formed by laser drilling of vias through the dielectric layers, which are then filled with conductive metal. A plurality of unfilled half-vias are arranged around edges of the laminated body adjacent external contact pads. Half-vias are formed by laser or mechanical drilling along scribe lines before singulation of packages. Surface plating of the half-vias comprises a solder wettable material. The half-vias are unfilled to form a wettable flank which allows for lateral wicking of solder during surface mounting, to facilitate optical inspection of solder reliability.

公开(公告)号：US20230111992A1

公开(公告)日：2023-04-13

申请号：US17497233

申请日：2021-10-08

Applicant: GaN Systems Inc.

Inventor： Xuechao LIU ,  Di CHEN ,  Yajie QIU

IPC: H02M1/42 ,  H02M3/335

Abstract: An AC/DC Switching Mode Power Supply (SMPS) comprises a PFC stage, an isolated LLC DC/DC converter stage, and a control circuit that provides feedback/control signals to PFC and LLC controllers, to enable a plurality of operating modes, dependent on a sensed peak AC input voltage and required output voltage Vo. The PFC provides a first DC bus voltage Vdc (e.g. 200V) for low line AC input and a second DC bus voltage (e.g. 400V) for high line or universal AC input. A multi-mode LLC converter is operable in a half-bridge mode or a full-bridge mode. For low line AC input, output voltage Vo, and PFC output Vdc, the LLC operates in full-bridge mode; for high line input, output voltage Vo and PFC output 2×Vdc, the LLC operates in half-bridge mode; for universal AC input, output voltage 2×Vo, and PFC output 2×Vdc, the LLC operates in full-bridge mode.

公开(公告)号：US20230402342A1

公开(公告)日：2023-12-14

申请号：US18094477

申请日：2023-01-09

Applicant: GaN Systems Inc.

Inventor： Di CHEN ,  Juncheng LU ,  Ahmad MIZAN ,  Ruoyu HOU ,  Abhinandan DIXIT

IPC: H01L23/367 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L23/3672 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers, and wherein a first thermal pad on one side of the package and a second thermal pad on an opposite side of the package provides for dual-side cooling. Example embodiments of the dual-side cooled package may be based on a bottom-side cooled layup with a primary bottom-side thermal pad and a secondary top-side thermal pad, or a top-side cooled layup with primary top-side thermal pad and a secondary bottom side thermal pad, using layups with or without a leadframe. For example, the power semiconductor switching device comprises a GaN power transistor, such as a GaN HEMT rated for operation at ≥100V or ≥600V, for switching tens or hundreds of Amps.

公开(公告)号：US20210398875A1

公开(公告)日：2021-12-23

申请号：US17465345

申请日：2021-09-02

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI ,  Peter Anthony DI MASO

IPC: H01L23/367 ,  H01L23/538 ,  H01L29/778 ,  H01L29/20 ,  H01L25/11 ,  H01L23/498

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

公开(公告)号：US20200185302A1

公开(公告)日：2020-06-11

申请号：US16705696

申请日：2019-12-06

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI ,  Peter Anthony DI MASO

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/498 ,  H01L29/20 ,  H01L25/11 ,  H01L29/778

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.