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    LOW POWER MULTIPLE BIT SENSE AMPLIFIER
    1.
    发明申请
    LOW POWER MULTIPLE BIT SENSE AMPLIFIER 有权
    低功率多位感应放大器

    公开(公告)号：US20090040821A1

    公开(公告)日：2009-02-12

    申请号：US12235134

    申请日：2008-09-22

    申请人： Girolamo Gallo ,  Giulio G. Marotta

    发明人： Girolamo Gallo ,  Giulio G. Marotta

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    摘要翻译： 用于多级闪存单元的读出放大器包括产生斜坡电压信号的电压斜坡发生器。 参考读出放大器将输入参考电流与斜坡电压信号产生的斜坡电流进行比较。 当斜坡电压信号大于参考电流时，输出锁存信号被切换。 读出放大器将输入位线电流与阈值进行比较，并在位线电流超过阈值时输出逻辑低电平。 读出放大器输出在锁存信号确定的时间被锁存在三个数字锁存器之一中。 编码器将来自三个数字锁存器的数据编码为两位输出数据。

    Low power multiple bit sense amplifier
    2.
    发明授权
    Low power multiple bit sense amplifier 有权

    公开(公告)号：US07440332B2

    公开(公告)日：2008-10-21

    申请号：US11958658

    申请日：2007-12-18

    申请人： Girolamo Gallo ,  Giulio G. Marotta

    发明人： Girolamo Gallo ,  Giulio G. Marotta

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    Low power multiple bit sense amplifier
    3.
    发明授权
    Low power multiple bit sense amplifier 有权
    低功率多位读出放大器

    公开(公告)号：US07701776B2

    公开(公告)日：2010-04-20

    申请号：US12235134

    申请日：2008-09-22

    申请人： Girolamo Gallo ,  Giulio G. Marotta

    发明人： Girolamo Gallo ,  Giulio G. Marotta

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/10 ,  G11C7/06 ,  G11C5/14

    CPC分类号： G11C7/062 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    摘要翻译： 用于多级闪存单元的读出放大器包括产生斜坡电压信号的电压斜坡发生器。 参考读出放大器将输入参考电流与斜坡电压信号产生的斜坡电流进行比较。 当斜坡电压信号大于参考电流时，输出锁存信号被切换。 读出放大器将输入位线电流与阈值进行比较，并在位线电流超过阈值时输出逻辑低电平。 读出放大器输出在锁存信号确定的时间被锁存在三个数字锁存器之一中。 编码器将来自三个数字锁存器的数据编码为两位输出数据。

    Low power multiple bit sense amplifier
    4.
    发明授权
    Low power multiple bit sense amplifier 有权
    低功率多位读出放大器

    公开(公告)号：US07324381B2

    公开(公告)日：2008-01-29

    申请号：US11416672

    申请日：2006-05-03

    申请人： Girolamo Gallo ,  Giulio G. Marotta

    发明人： Girolamo Gallo ,  Giulio G. Marotta

    IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    摘要翻译： 用于多级闪存单元的读出放大器包括产生斜坡电压信号的电压斜坡发生器。 参考读出放大器将输入参考电流与斜坡电压信号产生的斜坡电流进行比较。 当斜坡电压信号大于参考电流时，输出锁存信号被切换。 读出放大器将输入位线电流与阈值进行比较，并在位线电流超过阈值时输出逻辑低电平。 读出放大器输出在锁存信号确定的时间被锁存在三个数字锁存器之一中。 编码器将来自三个数字锁存器的数据编码为两位输出数据。

    LOW POWER MULTIPLE BIT SENSE AMPLIFIER
    7.
    发明申请
    LOW POWER MULTIPLE BIT SENSE AMPLIFIER 有权
    低功率多位感应放大器

    公开(公告)号：US20080094909A1

    公开(公告)日：2008-04-24

    申请号：US11958658

    申请日：2007-12-18

    申请人： Girolamo Gallo ,  Giulio Marotta

    发明人： Girolamo Gallo ,  Giulio Marotta

    IPC分类号： G11C16/06

    CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    摘要翻译： 用于多级闪存单元的读出放大器包括产生斜坡电压信号的电压斜坡发生器。 参考读出放大器将输入参考电流与斜坡电压信号产生的斜坡电流进行比较。 当斜坡电压信号大于参考电流时，输出锁存信号被切换。 读出放大器将输入位线电流与阈值进行比较，并在位线电流超过阈值时输出逻辑低电平。 读出放大器输出在锁存信号确定的时间被锁存在三个数字锁存器之一中。 编码器将来自三个数字锁存器的数据编码为两位输出数据。

    Variable impedence output buffer
    9.
    发明申请
    Variable impedence output buffer 有权

    公开(公告)号：US20060139051A1

    公开(公告)日：2006-06-29

    申请号：US11358235

    申请日：2006-02-21

    申请人： Girolamo Gallo ,  Giulio Marotta

    发明人： Girolamo Gallo ,  Giulio Marotta

    IPC分类号： H03K19/003

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K19/018585

    摘要： An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.