摘要:
A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.
摘要:
A system for permitting remote user access to regions of memory that have been exported for remote direct memory access purposes. The system supports dynamically changing access privileges to remote users without requiring intervention from an operating system. The system may include a memory region table and a memory window table for supporting address translations. Entries in the memory window table may include a region remote access key and a window remote access key. The memory region table may include fields for a physical address, an access value, a protection domain value, and a length of memory region.
摘要:
Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.
摘要:
A method for controlling sharing of resources in a multi-threaded environment includes entering a finite state machine state sequence; controlling resource-sharing threads using the finite state machine state sequence; and exiting the finite state machine state sequence when shared resource control is complete. A multi-threaded shared resource control system includes a finite state machine configured to control multi-threaded access to shared resources; a plurality of producer threads regulated by the finite state machine; and a plurality of consumer threads regulated by the finite state machine. A non-transitory computer usable medium having computer readable program code embodied therein for causing a computer system to execute a method for controlling sharing of resources in a multi-threaded environment includes entering a finite state machine state sequence; controlling resource-sharing threads using the finite state machine state sequence; and exiting the finite state machine state sequence when shared resource control is complete.
摘要:
A method for transmitting messages between two processes includes creating a communications channel between a first channel adapter coupled to a client process and a second channel adapter coupled to a remote process. The method further includes reading a request message at the first channel adapter, segmenting the request message into a series of packets, assigning a sequence number to each packet, and transmitting the packets in order to the second channel adapter through the communications channel. The method further includes receiving the packets at the second channel adapter and sending at least one acknowledgement message to the first channel adapter in response to the received packets. The acknowledgement message has a packet sequence number field containing a packet sequence number and a payload containing a message sequence number, wherein the message sequence number identifies a complete message last received at the second channel adapter and the packet sequence number identifies a packet last received at the second channel adapter.
摘要:
Collisions in access to a simulated device are avoided by reserving to one of two or more hardware simulation tests the simulated device. Deadlocks involving requests of multiple tests for reservation of devices are prevented by establishing the order in which such requests are served and requiring that a test must first relinquish reservation of all devices prior to reserving additional devices. Thus, when the additional requests are appended to a queue of pending reservation requests, no test whose requests follow the requests of a second test in the queue can reserve a device requested by the second test. In other words, the situation in which each of two or more tests has reserved a device, reservation of which is required by another of the two or more tests, cannot occur. Starvation is prevented by combining the sorted queue of each reservation phase into a sorted "round robin" arrangement. Specifically, each collection of requests of a reservation phase are sorted into a request arrival queue and, when the request arrival queue includes all requests of a particular reservation phase, the request arrival queue is appended to the pending request queue. Thus, the lowest priority request of a particular reservation phase of requests is given higher priority than the highest priority request of a subsequent reservation phase. In addition, repeatability of reservation request arbitration is achieved by sorting reservation requests in each request arrival queue according to the respective identifiers of the requesting tests.
摘要:
To simulate a bus of a circuit, a number of virtual bus stubs ("VBSs") each post simulated bus signals as a single step and execution of the simulation system which includes such a VBS continues. As a subsequent, separate step, the VBS substantially immediately thereafter reaps a resolved simulated bus state. Synchronization in such a system is achieved by grouping into zones all VBSs which collectively represent the simulated state of a single bus. Each VBS has one of four states, namely, reap running, reap stopped, post running, post stopped. When a VBS posts, it is determined whether any other VBS of the same zone has yet to reap a previously resolved simulated bus state. If such a VBS exists, the posting VBS moves from reap running state to a post stopped state and execution of the simulation system containing the posting VBS is suspended until the last VBS of a zone reaps the previously resolved simulated bus state. Otherwise, if all VBSs of the same zone have reaped the previously resolved simulated bus state, the posting VBS moves from a reap running state to a post running state and execution of the simulation system containing the posting VBS continues. When a VBS reaps, it is determined whether any other VBS of the same zone has yet to post simulated bus signals for the current resolution of the simulated bus state. If such a VBS exists, the reaping VBS moves from post running state to a reap stopped state and execution of the simulation system containing the reaping VBS is suspended until the last VBS of a zone posts simulated bus signals for the current resolution of the simulated bus state. Otherwise, if all VBSs of the same zone have reaped simulated bus signals for the current resolution of the simulated bus state, the reaping VBS moves from a post running state to a reap running state and execution of the simulation system containing the reaping VBS continues.
摘要:
An apparatus for linking a hot-plug device to a host includes a slave interface circuit for connection to the host; a master interface circuit for connection to the hot-plug device; and direction, data, and clock lines that link the master and slave interface circuits. A control logic circuit detects a Presence Detect signal on the direction line. A method of determining a connection between a host and a hot-plug device includes asserting a direction signal on a direction line to control a direction of a flow of data between the host and the hot-plug device; toggling the direction signal to indicate a presence of the hot-plug device; and indicating a disconnect after a given period of inactivity in the toggling. A method of linking a host and a hot-plug device interface circuit for connection to a hot-plug device includes asserting a Presence Detect signal on the direction line.
摘要:
A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes. Changes to the functional model designs necessitate changes to the subclasses, but the interface independent transaction classes maintain a consistent interface and allow the test code to be re-used with minimal changes.
摘要:
The synchronization state of each of a number of concurrently executing tests which interacts with a particular circuit simulation of one or more circuit simulations which collective simulate a circuit is represented and controlled by a respective local synchronization thread (“LST”) of a hub through which each test interacts with each circuit simulation. When in a synchronization state in which a test is permitted to interact with a particular circuit simulation, the LST corresponding to the test prevents the circuit simulation from advancing simulated time by acquisition by the LST of a hold lock on the circuit simulation. The LST releases the hold lock when the synchronization state of the test is a state in which the test cannot interact with the circuit simulation. Each test is permitted to interact with the circuit simulation in a particular state. When each test completes interaction with the circuit simulation, each test enters a barrier mechanism. The barrier mechanism is used to ensure that all tests which are to request reservations of devices of the circuit simulation have requested from the hub such reservations before any test proceeds. In this way, the hub can establish the order in which such requests are granted in a repeatable manner. As each test enters the barrier mechanism, execution of the test is suspended and a reference to the test is added to a thread list. When all tests which are to enter the barrier have done so, each thread identified by a reference on the thread list is awakened and execution of the test resumes.