Fully Programmable Parallel PRBS Generator
    1.
    发明申请
    Fully Programmable Parallel PRBS Generator 有权
    全可编程并行PRBS发生器

    公开(公告)号:US20130055039A1

    公开(公告)日:2013-02-28

    申请号:US13221543

    申请日:2011-08-30

    申请人: Glenn A. Dearth

    发明人: Glenn A. Dearth

    IPC分类号: G11C29/52 G06F11/00 G06F7/58

    摘要: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.

    摘要翻译: 公开了一种伪随机比特流生成器,其具有直到CSR的支持宽度的完全可编程的伪随机多项式,完全可编程的抽头选择,用于提供任何指定的发生器状态抽头的组合,以及完全可编程的并行序列生成, 计算顺序位,以及序列发生器每个时钟的进位数。

    System for accessing a region of memory using remote address translation and using a memory window table and a memory region table
    2.
    发明授权
    System for accessing a region of memory using remote address translation and using a memory window table and a memory region table 有权
    使用远程地址转换访问内存区域并使用内存窗口表和内存区域表的系统

    公开(公告)号:US06854032B2

    公开(公告)日:2005-02-08

    申请号:US10007154

    申请日:2001-12-04

    IPC分类号: G06F12/10 G06F12/14 G06F12/00

    CPC分类号: G06F12/1475 G06F12/1072

    摘要: A system for permitting remote user access to regions of memory that have been exported for remote direct memory access purposes. The system supports dynamically changing access privileges to remote users without requiring intervention from an operating system. The system may include a memory region table and a memory window table for supporting address translations. Entries in the memory window table may include a region remote access key and a window remote access key. The memory region table may include fields for a physical address, an access value, a protection domain value, and a length of memory region.

    摘要翻译: 允许远程用户访问已经导出用于远程直接存储器访问目的的存储器区域的系统。 系统支持动态更改对远程用户的访问权限,而无需操作系统的干预。 系统可以包括用于支持地址转换的存储器区域表和存储器窗口表。 存储器窗口表中的条目可以包括区域远程访问密钥和窗口远程访问密钥。 存储器区域表可以包括用于物理地址的字段,访问值,保护域值和存储器区域的长度。

    Method and Apparatus for Memory Access Delay Training
    3.
    发明申请
    Method and Apparatus for Memory Access Delay Training 有权
    存储器访问延迟训练的方法和装置

    公开(公告)号:US20130315014A1

    公开(公告)日:2013-11-28

    申请号:US13477642

    申请日:2012-05-22

    IPC分类号: G11C8/18

    摘要: Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.

    摘要翻译: 公开了用于训练用于在存储器子系统中启用数据选通信号的延迟的各种方法和装置实施例。 在一个实施例中,系统包括被配置为接收数据选通信号的存储器控​​制器。 存储器控制器包括训练电路。 训练电路包括:第一存储电路,被耦合以在数据输入端接收数据选通信号;以及训练单元,被配置为基于从第一触发器接收的输出信号调整 使能信号的相位直到使能信号的断言与数据选通信号中的前导码指示一致。

    Multi-threaded shared state variable control
    4.
    发明授权
    Multi-threaded shared state variable control 有权
    多线程共享状态变量控制

    公开(公告)号:US08201179B2

    公开(公告)日:2012-06-12

    申请号:US11417427

    申请日:2006-05-04

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526

    摘要: A method for controlling sharing of resources in a multi-threaded environment includes entering a finite state machine state sequence; controlling resource-sharing threads using the finite state machine state sequence; and exiting the finite state machine state sequence when shared resource control is complete. A multi-threaded shared resource control system includes a finite state machine configured to control multi-threaded access to shared resources; a plurality of producer threads regulated by the finite state machine; and a plurality of consumer threads regulated by the finite state machine. A non-transitory computer usable medium having computer readable program code embodied therein for causing a computer system to execute a method for controlling sharing of resources in a multi-threaded environment includes entering a finite state machine state sequence; controlling resource-sharing threads using the finite state machine state sequence; and exiting the finite state machine state sequence when shared resource control is complete.

    摘要翻译: 一种用于控制多线程环境中的资源共享的方法包括进入有限状态机状态序列; 使用有限状态机状态序列控制资源共享线程; 并在共享资源控制完成时退出有限状态机状态序列。 多线程共享资源控制系统包括被配置为控制对共享资源的多线程访问的有限状态机; 由有限状态机调节的多个生产者线程; 以及由有限状态机调节的多个消费者线程。 一种具有其中包含有计算机可读程序代码的非瞬时计算机可用介质,用于使计算机系统执行用于控制多线程环境中的资源共享的方法,包括进入有限状态机状态序列; 使用有限状态机状态序列控制资源共享线程; 并在共享资源控制完成时退出有限状态机状态序列。

    Mechanism for completing messages in memory
    5.
    发明授权
    Mechanism for completing messages in memory 有权
    在内存中完成消息的机制

    公开(公告)号:US06744765B1

    公开(公告)日:2004-06-01

    申请号:US09645864

    申请日:2000-08-24

    IPC分类号: H04L1228

    CPC分类号: H04L47/10 H04L47/34 H04L67/42

    摘要: A method for transmitting messages between two processes includes creating a communications channel between a first channel adapter coupled to a client process and a second channel adapter coupled to a remote process. The method further includes reading a request message at the first channel adapter, segmenting the request message into a series of packets, assigning a sequence number to each packet, and transmitting the packets in order to the second channel adapter through the communications channel. The method further includes receiving the packets at the second channel adapter and sending at least one acknowledgement message to the first channel adapter in response to the received packets. The acknowledgement message has a packet sequence number field containing a packet sequence number and a payload containing a message sequence number, wherein the message sequence number identifies a complete message last received at the second channel adapter and the packet sequence number identifies a packet last received at the second channel adapter.

    摘要翻译: 用于在两个进程之间传送消息的方法包括在耦合到客户端进程的第一通道适配器和耦合到远程进程的第二通道适配器之间建立通信通道。 该方法还包括在第一信道适配器处读取请求消息,将请求消息分割成一系列分组,向每个分组分配序列号,并通过通信信道向第二信道适配器发送分组。 该方法还包括在第二信道适配器处接收分组,并响应于所接收的分组向第一信道适配器发送至少一个确认消息。 确认消息具有分组序列号字段,其包含分组序列号和包含消息序列号的有效载荷,其中消息序列号标识在第二信道适配器上最后接收的完整消息,并且分组序列号标识最后在 第二个通道适配器。

    Method and system for preventing device access collision in a
distributed simulation executing in one or more computers including
concurrent simulated one or more devices controlled by concurrent one
or more tests
    6.
    发明授权
    Method and system for preventing device access collision in a distributed simulation executing in one or more computers including concurrent simulated one or more devices controlled by concurrent one or more tests 失效
    在一个或多个计算机中执行的分布式仿真中防止设备访问冲突的方法和系统,包括由并发的一个或多个测试控制的并发模拟的一个或多个设备

    公开(公告)号:US5812824A

    公开(公告)日:1998-09-22

    申请号:US621818

    申请日:1996-03-22

    IPC分类号: G06F11/22 G06F17/50 G06F15/00

    CPC分类号: G06F11/2273 G06F17/5022

    摘要: Collisions in access to a simulated device are avoided by reserving to one of two or more hardware simulation tests the simulated device. Deadlocks involving requests of multiple tests for reservation of devices are prevented by establishing the order in which such requests are served and requiring that a test must first relinquish reservation of all devices prior to reserving additional devices. Thus, when the additional requests are appended to a queue of pending reservation requests, no test whose requests follow the requests of a second test in the queue can reserve a device requested by the second test. In other words, the situation in which each of two or more tests has reserved a device, reservation of which is required by another of the two or more tests, cannot occur. Starvation is prevented by combining the sorted queue of each reservation phase into a sorted "round robin" arrangement. Specifically, each collection of requests of a reservation phase are sorted into a request arrival queue and, when the request arrival queue includes all requests of a particular reservation phase, the request arrival queue is appended to the pending request queue. Thus, the lowest priority request of a particular reservation phase of requests is given higher priority than the highest priority request of a subsequent reservation phase. In addition, repeatability of reservation request arbitration is achieved by sorting reservation requests in each request arrival queue according to the respective identifiers of the requesting tests.

    摘要翻译: 通过保留模拟设备的两个或多个硬件仿真测试中的一个来避免访问仿真设备的冲突。 通过确定提供这种请求的顺序来阻止涉及对设备预留的多次测试的请求的死锁,并要求测试必须首先在预留附加设备之前放弃所有设备的预留。 因此,当附加请求被附加到待处理的预留请求的队列时,没有其请求遵循队列中的第二测试的请求的测试可以预留由第二测试请求的设备。 换句话说,两个或更多个测试中的每一个已经保留了一个设备的情况,其中两个或更多个测试中的另一个测试需要其预约。 通过将每个预留阶段的排序队列组合成排序的“循环”排列来防止饥饿。 具体而言,预约阶段的每个请求集合被分类到请求到达队列中,并且当请求到达队列包括特定保留阶段的所有请求时,请求到达队列被附加到等待请求队列。 因此,请求的特定保留阶段的最低优先级请求被给予比后续保留阶段的最高优先级请求更高的优先级。 此外,通过根据请求测试的相应标识符对每个请求到达队列中的预约请求进行排序来实现预留请求仲裁的重复性。

    Deadlock avoidance mechanism for virtual bus distributed hardware
simulation
    7.
    发明授权
    Deadlock avoidance mechanism for virtual bus distributed hardware simulation 失效
    虚拟总线分布式硬件仿真的死锁避免机制

    公开(公告)号:US5907695A

    公开(公告)日:1999-05-25

    申请号:US621777

    申请日:1996-03-22

    申请人: Glenn A. Dearth

    发明人: Glenn A. Dearth

    IPC分类号: G06F17/50 G06F15/20

    CPC分类号: G06F17/5022

    摘要: To simulate a bus of a circuit, a number of virtual bus stubs ("VBSs") each post simulated bus signals as a single step and execution of the simulation system which includes such a VBS continues. As a subsequent, separate step, the VBS substantially immediately thereafter reaps a resolved simulated bus state. Synchronization in such a system is achieved by grouping into zones all VBSs which collectively represent the simulated state of a single bus. Each VBS has one of four states, namely, reap running, reap stopped, post running, post stopped. When a VBS posts, it is determined whether any other VBS of the same zone has yet to reap a previously resolved simulated bus state. If such a VBS exists, the posting VBS moves from reap running state to a post stopped state and execution of the simulation system containing the posting VBS is suspended until the last VBS of a zone reaps the previously resolved simulated bus state. Otherwise, if all VBSs of the same zone have reaped the previously resolved simulated bus state, the posting VBS moves from a reap running state to a post running state and execution of the simulation system containing the posting VBS continues. When a VBS reaps, it is determined whether any other VBS of the same zone has yet to post simulated bus signals for the current resolution of the simulated bus state. If such a VBS exists, the reaping VBS moves from post running state to a reap stopped state and execution of the simulation system containing the reaping VBS is suspended until the last VBS of a zone posts simulated bus signals for the current resolution of the simulated bus state. Otherwise, if all VBSs of the same zone have reaped simulated bus signals for the current resolution of the simulated bus state, the reaping VBS moves from a post running state to a reap running state and execution of the simulation system containing the reaping VBS continues.

    摘要翻译: 为了模拟电路的总线,多个虚拟总线存根(“VBS”)每个将模拟总线信号作为一个步骤,并且继续执行包括这样的VBS的模拟系统。 作为随后的单独步骤,VBS基本上立即收到解析的模拟总线状态。 这种系统中的同步通过将所有VBS组合成一个共同表示单个总线的模拟状态的区域来实现。 每个VBS都有四种状态之一,即收获运行,收获停止,后期运行,停止发布。 当VBS发布时,确定同一区域的任何其他VBS是否还没有获得先前解析的模拟总线状态。 如果存在这样的VBS,则发布VBS从收货运行状态移动到停止状态,并且暂停包含发布VBS的模拟系统的执行,直到区域的最后VBS收到先前解析的模拟总线状态为止。 否则,如果同一区域的所有VBS都获得先前解析的模拟总线状态,则发布VBS从收货运行状态移动到后运行状态,并且包含发布VBS的模拟系统的执行继续。 当VBS收到时,确定同一区域的任何其他VBS是否还没有发布模拟总线状态的当前分辨率的模拟总线信号。 如果存在这样的VBS,则VBS从后运行状态转移到收货停止状态,并且包含收货VBS的模拟系统的执行被暂停,直到区域的最后VBS向仿真总线的当前分辨率发布模拟总线信号 州。 否则,如果同一区域的所有VBS都获得模拟总线状态的当前分辨率的模拟总线信号,则收集VBS从后运行状态移动到收货运行状态,并且包含收货VBS的模拟系统的执行继续。

    Hot-plug link
    8.
    发明申请
    Hot-plug link 有权
    热插拔链接

    公开(公告)号:US20080046624A1

    公开(公告)日:2008-02-21

    申请号:US11506340

    申请日:2006-08-18

    IPC分类号: G06F13/00

    CPC分类号: G06F13/4072 G06F13/4081

    摘要: An apparatus for linking a hot-plug device to a host includes a slave interface circuit for connection to the host; a master interface circuit for connection to the hot-plug device; and direction, data, and clock lines that link the master and slave interface circuits. A control logic circuit detects a Presence Detect signal on the direction line. A method of determining a connection between a host and a hot-plug device includes asserting a direction signal on a direction line to control a direction of a flow of data between the host and the hot-plug device; toggling the direction signal to indicate a presence of the hot-plug device; and indicating a disconnect after a given period of inactivity in the toggling. A method of linking a host and a hot-plug device interface circuit for connection to a hot-plug device includes asserting a Presence Detect signal on the direction line.

    摘要翻译: 用于将热插拔设备连接到主机的设备包括用于连接到主机的从接口电路; 用于连接到热插拔设备的主接口电路; 以及链接主从接口电路的方向,数据和时钟线。 控制逻辑电路检测方向线上的存在检测信号。 确定主机和热插拔设备之间的连接的方法包括在方向线上断言方向信号以控制主机和热插拔设备之间的数据流的方向; 切换方向信号以指示热插拔设备的存在; 并指示在切换期间给定的不活动时间段之后断开连接。 将主机和用于连接到热插拔设备的热插拔设备接口电路连接的方法包括在方向线上断言存在检测信号。

    Interface independent test system
    9.
    发明授权
    Interface independent test system 有权
    接口独立测试系统

    公开(公告)号:US06421634B1

    公开(公告)日:2002-07-16

    申请号:US09262575

    申请日:1999-03-04

    IPC分类号: G06F9455

    CPC分类号: G06F17/5022

    摘要: A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes. Changes to the functional model designs necessitate changes to the subclasses, but the interface independent transaction classes maintain a consistent interface and allow the test code to be re-used with minimal changes.

    摘要翻译: 一种用于电路设计验证测试的系统和方法,使用独立于接口的类的结构来提供快速原型设计和设计修改,同时最大限度地提高测试代码的重用性。 电路仿真子系统与测试子系统接口。 测试子系统采用系统事务类来收集通用例程和指向设备事务的指针。 从系统事务类派生的一个或多个配置事务类定义模拟子系统内的功能模型之间的事务,并引起各个功能模型的实例化。 通过指向界面独立事务类的指针对功能模型执行操作,这些事务类定义了设备的接口。 操作通过接口独立事务类的子类映射到功能模型的当前设计。 对功能模型设计的更改需要对子类进行更改,但独立于接口的事务类保持一致的接口,并允许以最小的更改重新使用测试代码。

    Synchronization mechanism for distributed hardware simulation
    10.
    发明授权
    Synchronization mechanism for distributed hardware simulation 有权
    分布式硬件仿真同步机制

    公开(公告)号:US06345242B1

    公开(公告)日:2002-02-05

    申请号:US09639389

    申请日:2000-08-15

    IPC分类号: G06F945

    CPC分类号: G06F17/5022

    摘要: The synchronization state of each of a number of concurrently executing tests which interacts with a particular circuit simulation of one or more circuit simulations which collective simulate a circuit is represented and controlled by a respective local synchronization thread (“LST”) of a hub through which each test interacts with each circuit simulation. When in a synchronization state in which a test is permitted to interact with a particular circuit simulation, the LST corresponding to the test prevents the circuit simulation from advancing simulated time by acquisition by the LST of a hold lock on the circuit simulation. The LST releases the hold lock when the synchronization state of the test is a state in which the test cannot interact with the circuit simulation. Each test is permitted to interact with the circuit simulation in a particular state. When each test completes interaction with the circuit simulation, each test enters a barrier mechanism. The barrier mechanism is used to ensure that all tests which are to request reservations of devices of the circuit simulation have requested from the hub such reservations before any test proceeds. In this way, the hub can establish the order in which such requests are granted in a repeatable manner. As each test enters the barrier mechanism, execution of the test is suspended and a reference to the test is added to a thread list. When all tests which are to enter the barrier have done so, each thread identified by a reference on the thread list is awakened and execution of the test resumes.

    摘要翻译: 多个并发执行的测试中的每一个的同步状态由集线器模拟电路的一个或多个电路模拟的特定电路仿真相互作用,由集线器的相应本地同步线程(“LST”)表示和控制, 每个测试与每个电路模拟相互作用。 当处于允许测试与特定电路仿真相互作用的同步状态时,对应于该测试的LST防止电路模拟通过LST通过电路仿真中的保持锁获取来提前模拟时间。 当测试的同步状态是测试不能与电路仿真交互的状态时,LST释放保持锁定。 允许每个测试在特定状态下与电路仿真进行交互。 当每个测试完成与电路仿真的交互时,每个测试进入屏障机制。 屏障机制用于确保在任何测试进行之前,要求电路仿真设备的预留的所有测试从集线器请求此类预留。 以这种方式,集线器可以以可重复的方式建立授予这些请求的顺序。 当每个测试进入屏障机制时,测试的执行被暂停,并且对测试的引用被添加到线程列表中。 当进入屏障的所有测试都这样做时,线程列表上的引用标识的每个线程被唤醒,并且测试的执行恢复。