公开(公告)号：US06861308B2

公开(公告)日：2005-03-01

申请号：US10437530

申请日：2003-05-13

Applicant: Gregory D. U'Ren ,  Sy Vo

Inventor： Gregory D. U'Ren ,  Sy Vo

IPC: H01L20060101 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/8249 ,  H01L31/0328

CPC classification number: H01L21/8249 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661

Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.

Abstract translation: 所公开的实施例是用于制造SiGe层的方法，所述方法包括在第一压力下在单结晶区域和至少一个隔离区域上沉积硅缓冲层，其中硅缓冲层是连续的，即包括小的多晶粒， 在所述至少一个隔离区域上。 该方法还包括在第二压力下在硅缓冲层上形成硅锗层，其中硅锗层在至少一个隔离区域上也是连续的，即包含小的多晶粒。 在一个实施例中，第一压力小于第二压力。 在其他实施例中，根据上述方法制造结构。

公开(公告)号：US06514886B1

公开(公告)日：2003-02-04

申请号：US09667660

申请日：2000-09-22

Applicant: Gregory D. U'Ren

Inventor： Gregory D. U'Ren

IPC: H01L21469

CPC classification number: H01L21/02046 ,  C30B25/02 ,  C30B29/52 ,  H01L21/31116 ,  Y10S438/906

Abstract: According to the disclosed method, the surface of a semiconductor wafer is covered by a protective oxide. For example, the protective oxide can be silicon oxide and the semiconductor wafer can be a silicon wafer. The semiconductor wafer is then placed in a CVD reactor at a first temperature. For example, the first temperature can be approximately 650° C. Contaminants and the protective oxide are then removed from the surface of the semiconductor wafer at the first temperature. For example, contaminants and the protective oxide can be removed from the surface of a silicon wafer by using an etchant, such as Hydrogen Chloride (HCl), and a precursor, such as Dichlorosilane (SiH2Cl2 or “DCS”), in appropriate proportions. While contaminants and the protective oxide are being removed by the action of HCl and DCS, any silicon being removed from the surface of the silicon wafer, is being replenished so that there is no net change in the amount of silicon on the surface of the wafer. After removal of the contaminants and the protective oxide, epitaxial growth is performed on the surface of the semiconductor wafer at the first temperature. For example, silicon germanium epitaxial growth can be performed on the surface of a silicon wafer. A structure comprising an epitaxially grown region can be fabricated according to the disclosed method. For example, a silicon-germanium base region of a heterojunction bipolar transistor can be formed on a silicon surface prepared according to the disclosed method.

Abstract translation: 根据所公开的方法，半导体晶片的表面被保护氧化物覆盖。 例如，保护氧化物可以是氧化硅，半导体晶片可以是硅晶片。 然后将半导体晶片置于第一温度的CVD反应器中。 例如，第一温度可以是约650℃。然后在第一温度下将污染物和保护性氧化物从半导体晶片的表面去除。 例如，可以通过使用诸如氯化氢（HCl）的蚀刻剂和诸如二氯硅烷（SiH 2 Cl 2或“DCS”）的前体以适当比例从硅晶片的表面除去污染物和保护性氧化物。 虽然通过HCl和DCS的作用去除污染物和保护性氧化物，但是从硅晶片的表面除去的任何硅被补充，使得晶片表面上的硅量没有净变化 。 在除去污染物和保护氧化物之后，在第一温度下对半导体晶片的表面进行外延生长。 例如，可以在硅晶片的表面上进行硅锗外延生长。 可以根据所公开的方法制造包含外延生长区的结构。 例如，可以在根据所公开的方法制备的硅表面上形成异质结双极晶体管的硅 - 锗基区。

公开(公告)号：US06365479B1

公开(公告)日：2002-04-02

申请号：US09667274

申请日：2000-09-22

Applicant: Gregory D. U'Ren

Inventor： Gregory D. U'Ren

IPC: H01L21331

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract translation: 在一个实施方案中，提供用于生长多晶硅 - 锗区和单晶硅 - 锗区的前体气体。 前体气体可以是例如GeH 4。 多晶硅锗区可以是例如异质结双极晶体管中的基极接触，而单晶硅 - 锗区可以是例如异质结双极晶体管中的基极。 多晶硅锗区域可以在一定温度和一定压力的前体气体的质量控制模式下生长，同时可以在相同温度的动态控制模式下同时生长单晶硅 - 锗区域， 相同的前体气体压力。 所公开的实施例导致独立于单晶硅 - 锗的生长来控制多晶硅 - 锗的生长。

公开(公告)号：US07580172B2

公开(公告)日：2009-08-25

申请号：US11540485

申请日：2006-09-29

Applicant: Alan G. Lewis ,  Manish Kothari ,  John Batey ,  Teruo Sasagawa ,  Ming-Hau Tung ,  Gregory D. U'Ren ,  Stephen Zee

Inventor： Alan G. Lewis ,  Manish Kothari ,  John Batey ,  Teruo Sasagawa ,  Ming-Hau Tung ,  Gregory D. U'Ren ,  Stephen Zee

IPC: G02F1/03 ,  G02B26/00

CPC classification number: B81B7/0006 ,  B81B7/007 ,  B81B2201/047 ,  G02B26/001 ,  H02N1/006

Abstract: A microelectromechanical systems device having an electrical interconnect between circuitry outside the device and at least one of an electrode and a movable layer within the device. At least a portion of the electrical interconnect is formed from the same material as a conductive layer between the electrode and a mechanical layer of the device. In an embodiment, this conductive layer is a sacrificial layer that is subsequently removed to form a cavity between the electrode and the movable layer. The sacrificial layer is preferably formed of molybdenum, doped silicon, tungsten, or titanium. According to another embodiment, the conductive layer is a movable reflective layer that preferably comprises aluminum.

Abstract translation: 一种微机电系统装置，其具有在所述装置外部的电路和所述装置内的电极和可移动​​层中的至少一个之间的电互连。 电互连的至少一部分由与电极和器件的机械层之间的导电层相同的材料形成。 在一个实施例中，该导电层是牺牲层，其随后被去除以在电极和可移动​​层之间形成空腔。 牺牲层优选由钼，掺杂硅，钨或钛形成。 根据另一实施例，导电层是优选包括铝的可移动反射层。

公开(公告)号：US07078744B1

公开(公告)日：2006-07-18

申请号：US10888406

申请日：2004-07-10

Applicant: Gregory D. U'Ren

Inventor： Gregory D. U'Ren

IPC: H01L31/0328

CPC classification number: H01L29/66242 ,  H01L29/0804

Abstract: A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.

Abstract translation: 所公开的实施例是一种用于制造发射极结构的方法，包括在发射器窗口开口和基极上共形沉积未掺杂的多晶硅层的步骤。 接下来，掺杂多晶硅层被非共面沉积在未掺杂的层上。 此后，重复保形沉积未掺杂多晶硅层和非保形沉积掺杂多晶硅层的步骤，直到填充发射器窗口。 该方法还可以包括活化掺杂剂的步骤。 在另一个实施例中，根据上述方法制造发射极结构。

公开(公告)号：US07183627B2

公开(公告)日：2007-02-27

申请号：US10054438

申请日：2002-01-22

Applicant: Gregory D. U'ren

Inventor： Gregory D. U'ren

IPC: H01L27/082

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract translation: 在一个实施方案中，提供用于生长多晶硅 - 锗区和单晶硅 - 锗区的前体气体。 前体气体可以是例如GeH 4 N 4。 多晶硅锗区可以是例如异质结双极晶体管中的基极接触，而单晶硅 - 锗区可以是例如异质结双极晶体管中的基极。 多晶硅锗区域可以在一定温度和一定压力的前体气体的质量控制模式下生长，同时可以在相同温度的动态控制模式下同时生长单晶硅 - 锗区域， 相同的前体气体压力。 所公开的实施例导致独立于单晶硅 - 锗的生长来控制多晶硅 - 锗的生长。

公开(公告)号：US07064073B1

公开(公告)日：2006-06-20

申请号：US10434961

申请日：2003-05-09

Applicant: Gregory D. U'ren

Inventor： Gregory D. U'ren

IPC: H01L21/302

CPC classification number: C23C16/4405

Abstract: According to one embodiment, a method for reducing contaminants in a reactor chamber is disclosed where the method comprises a step of etching the reactor chamber, which can comprise, for example, a dry etch process performed with hydrogen and HCL. Next, the reactor chamber is baked, which can comprise, for example, baking with hydrogen. Thereafter, an undoped semiconductor layer, such as an undoped silicon layer, is deposited in the reactor chamber to form a sacrificial semiconductor layer, for example, a sacrificial silicon layer. Then, the sacrificial semiconductor layer, for example, the sacrificial silicon layer, is removed from the reactor chamber. The removal step can comprise, for example, a dry etch process performed with HCL. In another embodiment, a wafer is fabricated in a reactor chamber that is substantially free of contaminants due to the implementation of the above method.

Abstract translation: 根据一个实施例，公开了一种用于减少反应器室中的污染物的方法，其中该方法包括蚀刻反应器室的步骤，其可以包括例如用氢和HCL进行的干蚀刻工艺。 接下来，将反应器室烘烤，其可以包括例如用氢气烘烤。 此后，将未掺杂的半导体层，例如未掺杂的硅层沉积在反应器室中以形成牺牲半导体层，例如牺牲硅层。 然后，将牺牲半导体层，例如牺牲硅层从反应器室中移除。 去除步骤可以包括例如用HCL进行的干蚀刻工艺。 在另一个实施方案中，由于实施上述方法，晶片被制造在基本上不含污染物的反应器室中。

公开(公告)号：US07132700B1

公开(公告)日：2006-11-07

申请号：US10915797

申请日：2004-08-11

Applicant: Gregory D. U'Ren ,  Sy Vo

Inventor： Gregory D. U'Ren ,  Sy Vo

IPC: H01L31/072

CPC classification number: H01L21/8249 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661

Abstract: A disclosed embodiment is a method for fabricating a structure in a semiconductor die, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.

Abstract translation: 所公开的实施例是用于在半导体管芯中制造结构的方法，所述方法包括在第一压力下在单个晶体区域和至少一个隔离区域上沉积硅缓冲层，其中硅缓冲层是连续的，即包括小的 多晶粒，在至少一个隔离区域上。 该方法还包括在第二压力下在硅缓冲层上形成硅锗层，其中硅锗层在至少一个隔离区域上也是连续的，即包含小的多晶粒。 在一个实施例中，第一压力小于第二压力。 在其他实施例中，根据上述方法制造结构。

公开(公告)号：US06797578B1

公开(公告)日：2004-09-28

申请号：US10437723

申请日：2003-05-13

Applicant: Gregory D. U'Ren

Inventor： Gregory D. U'Ren

IPC: H01L21331

CPC classification number: H01L29/66242 ,  H01L29/0804

Abstract: A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.

Abstract translation: 所公开的实施例是一种用于制造发射极结构的方法，包括在发射器窗口开口和基极上共形沉积未掺杂的多晶硅层的步骤。 接下来，掺杂多晶硅层被非共面沉积在未掺杂的层上。 此后，重复保形沉积未掺杂多晶硅层和非保形沉积掺杂多晶硅层的步骤，直到填充发射器窗口。 该方法还可以包括活化掺杂剂的步骤。 在另一个实施例中，根据上述方法制造发射极结构。

公开(公告)号：US06580104B1

公开(公告)日：2003-06-17

申请号：US10114749

申请日：2002-04-01

Applicant: Gregory D. U'Ren

Inventor： Gregory D. U'Ren

IPC: H01L2710

CPC classification number: H01L21/02046 ,  C30B25/02 ,  C30B29/52 ,  H01L21/31116 ,  Y10S438/906

Abstract: According to the disclosed method, the surface of a semiconductor wafer is covered by a protective oxide. The semiconductor wafer is then placed in a CVD reactor at a first temperature. Contaminants and the protective oxide are then removed from the surface of the semiconductor wafer at the first temperature. While contaminants and the protective oxide are being removed by the action of HCl and DCS, any silicon being removed from the surface of the silicon wafer, is being replenished so that there is no net change in the amount of silicon on the surface of the water. After removal of the contaminants and the protective oxide, epitaxial growth is performed on the surface of the semiconductor wafer at the first temperature. A structure comprising an epitaxially grown region can be fabricated according to the disclosed method.

Abstract translation: 根据所公开的方法，半导体晶片的表面被保护氧化物覆盖。 然后将半导体晶片置于第一温度的CVD反应器中。 然后在第一温度下从半导体晶片的表面除去污染物和保护性氧化物。 虽然通过HCl和DCS的作用去除污染物和保护性氧化物，但是从硅晶片的表面除去的任何硅被补充，使得水的表面上的硅量没有净变化 。 在除去污染物和保护氧化物之后，在第一温度下对半导体晶片的表面进行外延生长。 可以根据所公开的方法制造包含外延生长区的结构。