公开(公告)号：US08748277B2

公开(公告)日：2014-06-10

申请号：US13613520

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08598670B2

公开(公告)日：2013-12-03

申请号：US12943330

申请日：2010-11-10

申请人： Akira Ito ,  Henry Kuo-Shun Chen

发明人： Akira Ito ,  Henry Kuo-Shun Chen

IPC分类号： H01L21/02

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

摘要翻译： 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

公开(公告)号：US20130087886A1

公开(公告)日：2013-04-11

申请号：US13270452

申请日：2011-10-11

申请人： Xiangdong Chen ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.

摘要翻译： 根据一个示例性实施例，半导体管芯中的金属氧化物金属（MOM）电容器包括第一多个电容器板和第二多个电容器板，第二多个电容器板共享平行于第一金属化层 半导体芯片。 MOM电容器还包括在第一多个电容器板和第二多个电容器板之间的局部层间电介质。 第一和第二多个电容器板由局部互连金属制成，用于连接形成在位于第一金属化层下方的半导体管芯的器件层中的器件。

公开(公告)号：US20130017658A1

公开(公告)日：2013-01-17

申请号：US13613520

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US20110169079A1

公开(公告)日：2011-07-14

申请号：US12657162

申请日：2010-01-14

申请人： Akira Ito ,  Henry Kuo-Shun Chen ,  Bruce Chih-Chieh Shen

发明人： Akira Ito ,  Henry Kuo-Shun Chen ,  Bruce Chih-Chieh Shen

IPC分类号： H01L29/78 ,  H01L21/30

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device having an overlapping multi-well implant comprises an isolation structure formed in a semiconductor body, a first well implant formed in the semiconductor body surrounding the isolation structure, and a second well implant overlapping at least a portion of the first well implant. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise a gate formed over the semiconductor body adjacent to the isolation structure, wherein the first well implant extends a first lateral distance under the gate and the second well implant extends a second lateral distance under the gate, and wherein the first and second lateral distances may be different. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including a power management circuit or a power amplifier.

摘要翻译： 根据一个实施例，具有重叠多阱注入的半导体器件包括形成在半导体本体中的隔离结构，形成在半导体主体中的围绕隔离结构的第一阱注入，以及重叠至少部分 第一口植入物。 所公开的可以是NMOS或PMOS器件的半导体器件还可以包括形成在半导体主体上方的与隔离结构相邻的栅极，其中第一阱注入在栅极下延伸第一横向距离，第二阱注入延伸一个 栅极下方的第二横向距离，并且其中第一和第二横向距离可以不同。 在一个实施例中，所公开的半导体器件被制造为包括功率管理电路或功率放大器的集成电路的一部分。

公开(公告)号：US20110057271A1

公开(公告)日：2011-03-10

申请号：US12943330

申请日：2010-11-10

申请人： Akira ITO ,  Henry Kuo-Shun CHEN

发明人： Akira ITO ,  Henry Kuo-Shun CHEN

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

摘要翻译： 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

公开(公告)号：US09041153B2

公开(公告)日：2015-05-26

申请号：US13248823

申请日：2011-09-29

申请人： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

发明人： Xiangdong Chen ,  Henry Kuo-Shun Chen ,  Wei Xia ,  Bruce Chih-Chieh Shen

IPC分类号： H01L29/92 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.

摘要翻译： 根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器 形成在底部电容器电极上的层间势垒电介质上的电极。 顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。 在一个实施例中，底部电容器电极由栅极金属形成。 该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

公开(公告)号：US08717137B2

公开(公告)日：2014-05-06

申请号：US11443171

申请日：2006-05-31

申请人： Henry Kuo-Shun Chen ,  Guang-Jye Shiau ,  Akira Ito

发明人： Henry Kuo-Shun Chen ,  Guang-Jye Shiau ,  Akira Ito

IPC分类号： H01F5/00

CPC分类号： H01L28/10 ,  H01F5/00 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/10 ,  H01L24/13 ,  H01L27/08 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

摘要： A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.

摘要翻译： 一种系统和方法利用倒装芯片或引线键合封装中的再分布层，其也用于将信号路由到凸点，作为用于构建片上电感器的层或多层片上层 电感。 在一个示例中，再分布层被双层钝化包围，以保护它，并且从环境形成的电感器从其环境中分离出来并将其与其形成的电感器从其下方的金属层隔离开来。

公开(公告)号：US08269275B2

公开(公告)日：2012-09-18

申请号：US12589357

申请日：2009-10-21

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08048765B2

公开(公告)日：2011-11-01

申请号：US12583977

申请日：2009-08-28

申请人： Xiangdong Chen ,  Bruce Chih-Chieh Shen ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Bruce Chih-Chieh Shen ,  Henry Kuo-Shun Chen

IPC分类号： H01L21/76

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/165 ,  H01L29/267 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/7848

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.