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    Field transistor structure manufactured using gate last process
    3.
    发明授权
    Field transistor structure manufactured using gate last process 有权
    使用门最后工艺制造的场晶体管结构

    公开(公告)号：US08841674B2

    公开(公告)日：2014-09-23

    申请号：US13174083

    申请日：2011-06-30

    申请人： Chao-Yang Lu ,  Guang-Jye Shiau ,  Akira Ito

    发明人： Chao-Yang Lu ,  Guang-Jye Shiau ,  Akira Ito

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/7839 ,  G11C17/16

    摘要： According to embodiments of the invention, a field transistor structure is provided. The field transistor structure includes a semiconductor substrate, a metal gate, a polycrystalline silicon (polysilicon) layer, and first and second metal portions. The polysilicon layer has first, second, third, and fourth sides and is disposed between the semiconductor substrate on the first side and the metal gate on the second side. The polysilicon layer is also disposed between the first and second metal portions on the third and fourth sides. According to some embodiments of the present invention, the field transistor structure may also include a thin metal layer disposed between the polysilicon layer and the semiconductor substrate. The thin metal layer may be electronically coupled to each of the first and second metal portions.

    摘要翻译： 根据本发明的实施例，提供了场晶体管结构。 场晶体管结构包括半导体衬底，金属栅极，多晶硅（多晶硅）层以及第一和第二金属部分。 多晶硅层具有第一，第二，第三和第四边，并且设置在第一侧的半导体衬底和第二侧上的金属栅极之间。 多晶硅层也设置在第三和第四侧上的第一和第二金属部分之间。 根据本发明的一些实施例，场晶体管结构还可以包括设置在多晶硅层和半导体衬底之间的薄金属层。 薄金属层可以电连接到第一和第二金属部分中的每一个。

    FIELD TRANSISTOR STRUCTURE MANUFACTURED USING GATE LAST PROCESS
    5.
    发明申请
    FIELD TRANSISTOR STRUCTURE MANUFACTURED USING GATE LAST PROCESS 有权
    采用闸门过程制造的现场晶体管结构

    公开(公告)号：US20130001574A1

    公开(公告)日：2013-01-03

    申请号：US13174083

    申请日：2011-06-30

    申请人： Chao-Yang Lu ,  Guang-Jye Shiau ,  Akira Ito

    发明人： Chao-Yang Lu ,  Guang-Jye Shiau ,  Akira Ito

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/7839 ,  G11C17/16

    摘要： According to embodiments of the invention, a field transistor structure is provided. The field transistor structure includes a semiconductor substrate, a metal gate, a polycrystalline silicon (polysilicon) layer, and first and second metal portions. The polysilicon layer has first, second, third, and fourth sides and is disposed between the semiconductor substrate on the first side and the metal gate on the second side. The polysilicon layer is also disposed between the first and second metal portions on the third and fourth sides. According to some embodiments of the present invention, the field transistor structure may also include a thin metal layer disposed between the polysilicon layer and the semiconductor substrate. The thin metal layer may be electronically coupled to each of the first and second metal portions.

    摘要翻译： 根据本发明的实施例，提供了场晶体管结构。 场晶体管结构包括半导体衬底，金属栅极，多晶硅（多晶硅）层以及第一和第二金属部分。 多晶硅层具有第一，第二，第三和第四边，并且设置在第一侧的半导体衬底和第二侧上的金属栅极之间。 多晶硅层也设置在第三和第四侧上的第一和第二金属部分之间。 根据本发明的一些实施例，场晶体管结构还可以包括设置在多晶硅层和半导体衬底之间的薄金属层。 薄金属层可以电连接到第一和第二金属部分中的每一个。

    Transistor having reduced channel dopant fluctuation
    7.
    发明申请
    Transistor having reduced channel dopant fluctuation 审中-公开
    具有减小的沟道掺杂剂波动的晶体管

    公开(公告)号：US20080067589A1

    公开(公告)日：2008-03-20

    申请号：US11524721

    申请日：2006-09-20

    申请人： Akira Ito ,  Henry Kuoshun Chen ,  Guang-Jye Shiau

    发明人： Akira Ito ,  Henry Kuoshun Chen ,  Guang-Jye Shiau

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78 ,  H01L29/66575

    摘要： According to one exemplary embodiment, a transistor includes a source and a drain separated by a channel. The transistor further includes a gate dielectric layer situated over the channel. The channel is situated in a well formed in a substrate. A pocket implant is not formed between the source and the drain so as to reduce dopant fluctuation in the channel, thereby reducing transistor mismatch. According to this exemplary embodiment, an LDD implant is not formed between the source and the drain so as to further reduce the dopant fluctuation in the channel.

    摘要翻译： 根据一个示例性实施例，晶体管包括由沟道分离的源极和漏极。 晶体管还包括位于通道上方的栅极电介质层。 通道位于形成在基底中的阱中。 在源极和漏极之间不形成口袋注入，以减少沟道中的掺杂剂波动，从而减少晶体管失配。 根据该示例性实施例，在源极和漏极之间不形成LDD注入，以进一步减小沟道中的掺杂剂波动。