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    Semiconductor device with increased breakdown voltage
    2.
    发明申请
    Semiconductor device with increased breakdown voltage 有权
    半导体器件具有增加的击穿电压

    公开(公告)号：US20080023760A1

    公开(公告)日：2008-01-31

    申请号：US11580961

    申请日：2006-10-16

    申请人： Akira Ito ,  Henry Kuo-Shun Chen

    发明人： Akira Ito ,  Henry Kuo-Shun Chen

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

    摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-Well regions adjacent to one another without an isolation region in between.

    摘要翻译： 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

    Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS)
    4.
    发明申请
    Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS) 审中-公开
    基于横沟扩散金属氧化物半导体（LDMOS）的浅沟槽隔离（STI）

    公开(公告)号：US20080246080A1

    公开(公告)日：2008-10-09

    申请号：US12155628

    申请日：2008-06-06

    申请人： Akira Ito ,  Henry Kuo-Shun Chen

    发明人： Akira Ito ,  Henry Kuo-Shun Chen

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659

    摘要： An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device further includes a shallow trench isolation (STI) region to increase the resistance from the drain region to the source region. The STI region includes a first side vertically aligned with a second side of the gate region. The STI region extends from the first side to a second side in contact with a second side of the drain region. The breakdown voltage of the n-type semiconductor device is directly proportional to a vertical length, or a depth, of the first side and/or the second side of the STI region. The horizontal length, or distance from the first side to the second side, of the STI region does not substantially contribute to the breakdown voltage of the semiconductor device. As a result, a conventional CMOS logic foundry technology may fabricate the STI region of the semiconductor device using a low operating voltage process minimum design rule.

    摘要翻译： 公开了一种用于增加半导体器件的击穿电压的装置。 半导体器件包括表示源极区的第一重掺杂区域。 第二重掺杂区域表示半导体器件的漏极区域。 第三重掺杂区域表示半导体器件的栅极区域。 半导体器件还包括浅沟槽隔离（STI）区域，以增加从漏区到源极区的电阻。 STI区域包括与栅极区域的第二侧垂直对准的第一侧面。 STI区从第一侧延伸到与漏区的第二侧接触的第二侧。 n型半导体器件的击穿电压与STI区域的第一侧和/或第二面的垂直长度或深度成正比。 STI区域的水平长度或从第一侧到第二侧的距离基本上不会有助于半导体器件的击穿电压。 结果，传统的CMOS逻辑铸造技术可以使用低工作电压工艺最小设计规则来制造半导体器件的STI区域。

    Semiconductor device with increased breakdown voltage
    5.
    发明授权
    Semiconductor device with increased breakdown voltage 有权
    具有提高击穿电压的半导体器件

    公开(公告)号：US07855414B2

    公开(公告)日：2010-12-21

    申请号：US11580961

    申请日：2006-10-16

    申请人： Akira Ito ,  Henry Kuo-Shun Chen

    发明人： Akira Ito ,  Henry Kuo-Shun Chen

    IPC分类号： H01L29/94 ,  H01L29/76

    CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

    摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

    摘要翻译： 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

    Semiconductor device with increased breakdown voltage
    6.
    发明授权
    Semiconductor device with increased breakdown voltage 有权
    半导体器件具有增加的击穿电压

    公开(公告)号：US08598670B2

    公开(公告)日：2013-12-03

    申请号：US12943330

    申请日：2010-11-10

    申请人： Akira Ito ,  Henry Kuo-Shun Chen

    发明人： Akira Ito ,  Henry Kuo-Shun Chen

    IPC分类号： H01L21/02

    CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

    摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

    摘要翻译： 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

    Semiconductor device having an overlapping multi-well implant and method for fabricating same
    7.
    发明申请
    Semiconductor device having an overlapping multi-well implant and method for fabricating same 审中-公开
    具有重叠多孔注入的半导体器件及其制造方法

    公开(公告)号：US20110169079A1

    公开(公告)日：2011-07-14

    申请号：US12657162

    申请日：2010-01-14

    申请人： Akira Ito ,  Henry Kuo-Shun Chen ,  Bruce Chih-Chieh Shen

    发明人： Akira Ito ,  Henry Kuo-Shun Chen ,  Bruce Chih-Chieh Shen

    IPC分类号： H01L29/78 ,  H01L21/30

    CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7835

    摘要： According to one embodiment, a semiconductor device having an overlapping multi-well implant comprises an isolation structure formed in a semiconductor body, a first well implant formed in the semiconductor body surrounding the isolation structure, and a second well implant overlapping at least a portion of the first well implant. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise a gate formed over the semiconductor body adjacent to the isolation structure, wherein the first well implant extends a first lateral distance under the gate and the second well implant extends a second lateral distance under the gate, and wherein the first and second lateral distances may be different. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including a power management circuit or a power amplifier.

    摘要翻译： 根据一个实施例，具有重叠多阱注入的半导体器件包括形成在半导体本体中的隔离结构，形成在半导体主体中的围绕隔离结构的第一阱注入，以及重叠至少部分 第一口植入物。 所公开的可以是NMOS或PMOS器件的半导体器件还可以包括形成在半导体主体上方的与隔离结构相邻的栅极，其中第一阱注入在栅极下延伸第一横向距离，第二阱注入延伸一个 栅极下方的第二横向距离，并且其中第一和第二横向距离可以不同。 在一个实施例中，所公开的半导体器件被制造为包括功率管理电路或功率放大器的集成电路的一部分。