公开(公告)号：US5996050A

公开(公告)日：1999-11-30

申请号：US904434

申请日：1997-07-31

申请人： Hamilton B. Carter ,  William M. Lowe

发明人： Hamilton B. Carter ,  William M. Lowe

IPC分类号： G06F12/08

CPC分类号： G06F12/0835 ,  G06F11/221 ,  G06F2212/1032

摘要： A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address and data contained in each cache line and a flag indicating the state of the cache line (e.g., MESI state, or other cache coherency protocol state) is utilized. In addition, the cache model object also holds a dynamically allocated list (the cycle list) of bus cycles. This list is used to store pointers to non-cache bus cycles initiated in the multi-bus system. Cache bus cycles can update the state of the cache model object and can also instruct the cache model to perform coherency tests on pending non-cache bus cycles in the cycle list. When all protocol tests for a non-cache bus cycle have been successfully completed, no further coherency tests are performed on that bus cycle. Cache master verification is also achieved by polling the cache model to determine source of target resolution cycles for a bus cycle initiated by bus masters. Thus, cache coherency and cache controller operations are efficiently checked.

摘要翻译： 公开了一种提供高速缓存一致性错误检测的方法，以及高速缓存主机对低效高速缓存使用的检测。 使用具有用于包含在每个高速缓存行中的地址和数据的高速缓存的模型以及指示高速缓存行的状态的标志（例如，MESI状态或其他高速缓存一致性协议状态）。 另外，缓存模型对象还保存了一个动态分配的总线周期列表（循环列表）。 该列表用于存储在多总线系统中启动的非高速缓存总线周期的指针。 缓存总线周期可以更新缓存模型对象的状态，并且还可以指示高速缓存模型对循环列表中的未缓存的非高速缓存总线周期执行一致性测试。 当非高速缓存总线周期的所有协议测试都已经成功完成时，在该总线周期内不进行进一步的一致性测试。 高速缓存主验证也通过轮询高速缓存模型来确定由总线主机启动的总线周期的目标分辨率周期的来源。 因此，高效地检查高速缓存一致性和高速缓存控制器操作。

公开(公告)号：US5913043A

公开(公告)日：1999-06-15

申请号：US904501

申请日：1997-08-01

申请人： Hamilton B. Carter ,  William M. Lowe

发明人： Hamilton B. Carter ,  William M. Lowe

IPC分类号： G06F11/34 ,  G06F13/00

CPC分类号： G06F11/3409 ,  G06F11/349 ,  G06F11/3419 ,  G06F11/3447 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

摘要： A system and a method to monitor performance and resource utilization for a bus bridge in a computer system are described. All pertinent performance information for the bus bridge is stored in a statistics keeping or monitor object. A bus object is created for each bus in the system. Each bus cycle object receives the current cycle count and sends elapsed time information to the monitor object. A plurality of cycle list objects can also be used to track resource usage by sending messages to the monitor object indicating the type of cycles that enter the bus bridge. The monitor object then tracks the number of pending cycles that accumulate within the bus bridge. Thus, the statistics keeping object can indicate the current usage of each tracked resource.

摘要翻译： 描述了一种用于监视计算机系统中的总线桥的性能和资源利用的系统和方法。 总线桥的所有相关性能信息都存储在统计信息或监视对象中。 为系统中的每个总线创建总线对象。 每个总线周期对象接收当前循环计数，并将经过的时间信息发送给监视对象。 多个循环列表对象也可用于通过向监视对象发送指示进入总线桥的周期类型的消息来跟踪资源使用。 然后监视对象跟踪在总线桥内累积的待处理周期数。 因此，统计保持对象可以指示每个跟踪资源的当前使用。

公开(公告)号：US5930482A

公开(公告)日：1999-07-27

申请号：US904504

申请日：1997-07-31

申请人： Hamilton B. Carter ,  William M. Lowe

发明人： Hamilton B. Carter ,  William M. Lowe

IPC分类号： G06F11/267 ,  G06F13/40 ,  G06F17/50 ,  G06F13/00

CPC分类号： G06F11/221 ,  G06F13/4027 ,  G06F17/5022

摘要： A transaction checking system and method to verify bus bridges in multi-master bus systems are described. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a mechanism of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures.

摘要翻译： 描述了一种用于验证多主总线系统中总线桥的事务检查系统和方法。 为系统中的每个总线创建状态机模型。 启动器周期列表和目标周期列表存储对应的总线周期状态机对象，并根据总线信号转换其状态。 总线周期状态机为其他验证任务提供持久存储的机制。 总线桥模型可以存储用于总线桥的每个配置寄存器的副本，从而监视总线桥的当前状态。 避免了由于数据合并，数据崩溃和地址重映射引起的错误故障。 缓存模型和基于循环的消息传递系统提供正确的高速缓存主控操作的验证。 还可以检测到缓存一致性错误。 可以创建统计信息对象来监视和存储总线桥的所有相关性能信息。 事务检查系统可以以独立于设备的方式和更严格的验证来监视总线桥的状态。 基于循环的验证总线桥内部状态的方法可以有效地解决总线周期，从而更好地预测可能发生的故障。

公开(公告)号：US5958035A

公开(公告)日：1999-09-28

申请号：US903704

申请日：1997-07-31

申请人： Hamilton B. Carter ,  William M. Lowe

发明人： Hamilton B. Carter ,  William M. Lowe

IPC分类号： G06F11/267 ,  G06F11/28 ,  G06F11/34 ,  G06F13/14

CPC分类号： G06F11/221 ,  G06F11/349 ,  G06F11/28

摘要： In a computer system having a bus bridge connecting a plurality of system buses, a methodology for checking completion of a bus cycle in a bus bridge verification system is disclosed. The methodology verifies that the bus bridge is asserting proper signals for each bus protocol. As each bus cycle begins, a state machine object corresponding to that bus cycle is instantiated and each byte of said bus cycle state machine object is checked for resolution. A stimulator object may provide a bus stimulus to said bus cycle state machine object which may update its states in response thereto. Upon transitioning into its holding state, the bus cycle state machine object may verify that each byte of its transaction is accounted for and has been routed to the proper destination. The state machine object for a particular bus cycle may contain storage for that bus cycle's properties such as clock cycle number, cycle address, cycle type, cycle data and the status of byte enables. This methodology maintains a static bus cycle object that can determine if its transaction has been resolved. The cycle-based approach avoids instances of false failures arising from address remapping, byte merging or byte collapsing.

摘要翻译： 在具有连接多个系统总线的总线桥的计算机系统中，公开了一种在总线桥接验证系统中检查总线周期完成的方法。 该方法验证总线桥是否为每个总线协议确定适当的信号。 当每个总线周期开始时，对应于该总线周期的状态机对象被实例化，并检查所述总线周期状态机对象的每个字节的分辨率。 刺激器对象可以向所述总线周期状态机对象提供总线刺激，所述总线周期状态机对象可以响应于此来更新其状态。 在转换到其保持状态之后，总线周期状态机对象可以验证其交易的每个字节被计入并被路由到适当的目的地。 特定总线周期的状态机对象可能包含该总线周期属性的存储，如时钟周期数，周期地址，周期类型，周期数据和字节使能状态。 该方法维护一个可以确定其事务是否已解决的静态总线周期对象。 基于循环的方法避免了由于地址重映射，字节合并或字节折叠引起的虚假故障的实例。

公开(公告)号：US06073194A

公开(公告)日：2000-06-06

申请号：US161341

申请日：1998-09-25

申请人： William M. Lowe

发明人： William M. Lowe

IPC分类号： G06F11/267 ,  G06F13/40 ,  G06F17/50 ,  G06F17/00 ,  G01R31/00 ,  G06F11/00

CPC分类号： G06F13/4027 ,  G06F11/221 ,  G06F17/5022

摘要： A system and method for detecting timing-related functional problems in an HDL design of a computer system component are disclosed. A simulated model of the HDL design is supplied with a reference signal through a simulated bus. A bus transaction signal is then applied to the simulated model through the same or different simulated bus. The delay between the bus transaction signal and the reference signal is then varied over a range of values, and the simulated model's response to the bus transaction signal for each such delay value is received and analyzed by a transaction checker stored in the computer system memory. The duration of the bus transaction signal may also be varied. This methodology allows conversion of system waveform relationships, which could be observed on a physical system incorporating a manufactured version of the computer system component under test, into simulation waveforms with the same relative relationship. Problems that were once found only after the device was manufactured can now be detected prior to the manufacturing stage.

摘要翻译： 公开了一种用于检测计算机系统组件的HDL设计中的定时相关功能问题的系统和方法。 HDL设计的模拟模型通过仿真总线提供参考信号。 然后，通过相同或不同的模拟总线将总线事务信号应用于模拟模型。 然后，总线事务信号和参考信号之间的延迟在一个值的范围内变化，并且模拟模型对每个这样的延迟值对总线事务信号的响应由存储在计算机系统存储器中的事务检查器接收和分析。 总线事务信号的持续时间也可以变化。 该方法允许系统波形关系的转换，这可以在包含所测试的计算机系统组件的制造版本的物理系统上观察到具有相同相对关系的仿真波形。 现在可以在制造阶段之前检测到仅在设备制造后才发现的问题。

公开(公告)号：US5414745A

公开(公告)日：1995-05-09

申请号：US69521

申请日：1993-06-01

申请人： William M. Lowe

发明人： William M. Lowe

IPC分类号： H03K5/00 ,  H03K3/70 ,  H03K5/156 ,  H03K17/00 ,  H03K19/00 ,  G11C19/28

CPC分类号： H03K5/156 ,  H03K3/70

摘要： A clocking disable and enable circuit is provided having an input for receiving a clocking signal and another input for receiving a disable/enable signal. The disable and enable circuit provides a clocking disable/enable output from the circuit which is synchronized with the clocking signal during times in which the disable/enable signal is not activated. At times during which the disable/enable signal is activated, the clocking disable/enable signal transitions after at least a one half clocking period to a steady state value (either high or low voltage level). After the disable/enable signal becomes inactive again, clocking disable/enable signal automatically resynchronizes to the clocking signal. The clocking disable and enable circuit herein is well suited for providing glitch-free transition between a clocking state and a steady state to a synchronized digital or analog circuit which depends upon clocking synchronization for its operation. The clocking disable and enable circuit herein is also well suited for providing temporary halt to the connected digital or analog circuit as well as providing periods of selective demodulation associated with frequency tracking communication systems.

摘要翻译： 提供了具有用于接收时钟信号的输入和用于接收禁用/使能信号的另一个输入的时钟禁止和使能电路。 禁用和使能电路在禁用/使能信号未被激活的时间提供来自电路的时钟禁止/使能输出，其与时钟信号同步。 在禁用/使能信号被激活的时间，时钟禁止/使能信号在至少一个半个时钟周期之后转变到稳定状态值（高或低电压电平）。 禁用/使能信号再次变为无效后，时钟禁止/使能信号自动与时钟信号重新同步。 这里的时钟禁止和使能电路非常适合于在时钟状态和稳定状态之间提供无脉冲转换到依赖于其操作的时钟同步的同步数字或模拟电路。 这里的时钟禁止和使能电路也非常适合于暂时停止连接的数字或模拟电路，以及提供与频率跟踪通信系统相关的选择性解调周期。

公开(公告)号：US5583461A

公开(公告)日：1996-12-10

申请号：US308351

申请日：1994-09-19

申请人： William M. Lowe

发明人： William M. Lowe

IPC分类号： G01R31/30 ,  G06F1/08 ,  H03K5/13 ,  H03K3/284

CPC分类号： G01R31/30 ,  G06F1/08

摘要： An internal clock generation circuit is provided for receiving an external clock signal. Based upon the duration of each high and low pulse width of the external clock signal, the internal clock generation circuit selects one of two possible clock signals as an internal clock signal for connection to a load device. Selection is based upon whether the high and low pulse durations of the external clock signal exceed or are less than a threshold amount. If exceeded, the external clock signal connects a longer duration pulse width internal clock signal to the load device. If less than, the internal clock signal connects a shorter duration internal clock signal to the load device. Accordingly, the internal clock generation circuit allows for variability in the external clock signal frequency and duty cycle and correspondingly selects one of two (and possibly more) clock signals for connection to the load device. Detection and selectability allows for load device operation at speeds less than maximum designed amounts in order to salvage slower speed devices and improve wafer yield.

摘要翻译： 提供内部时钟发生电路用于接收外部时钟信号。 基于外部时钟信号的每个高和低脉冲宽度的持续时间，内部时钟产生电路选择两个可能的时钟信号之一作为连接到负载设备的内部时钟信号。 选择是基于外部时钟信号的高和低脉冲持续时间是否超过或小于阈值量。 如果超出，则外部时钟信号将较长持续时间的脉冲宽度内部时钟信号连接到负载设备。 如果小于，则内部时钟信号将较短持续时间的内部时钟信号连接到负载设备。 因此，内部时钟发生电路允许外部时钟信号频率和占空比的变化，并且相应地选择用于连接到负载装置的两个（也可能更多个）时钟信号中的一个。 检测和可选性允许以小于最大设计量的速度对负载装置进行操作，以便挽救较慢的速度装置并提高晶片产量。

公开(公告)号：US6058253A

公开(公告)日：2000-05-02

申请号：US760968

申请日：1996-12-05

申请人： William M. Lowe

发明人： William M. Lowe

IPC分类号： G06F11/267 ,  G06F11/00

CPC分类号： G06F11/2236

摘要： A method and apparatus are presented for performing intrusive testing in order to verify proper operation of a microprocessor "feature". The method includes providing a microprocessor model which includes a representation of the feature to be tested. The feature operates in one of several different operating modes as determined by the states of one or more control signals. Intruder logic, configured to restrict operation of the feature to a single desired operating mode, is introduced into the microprocessor model. The microprocessor model executes a testing program which requires operation of the feature and produces a result. The result produced by the microprocessor model is compared to an expected result. Any difference between the result produced by the microprocessor model and the expected result may be due to an error in feature hardware or the portion of the feature control circuitry associated with the selected operating mode. The microprocessor model may be a software implementation (i.e., a set of instructions) or a hardware implementation (i.e., a logic device).

摘要翻译： 提出了一种用于执行插入式测试以便验证微处理器“特征”的正确操作的方法和装置。 该方法包括提供一个微处理器模型，其包括要测试的特征的表示。 该特征以由一个或多个控制信号的状态确定的若干不同操作模式之一操作。 被配置为将特征的操作限制到单个期望操作模式的入侵者逻辑被引入到微处理器模型中。 微处理器模型执行一个测试程序，该测试程序需要操作该特征并产生结果。 将微处理器模型产生的结果与预期结果进行比较。 由微处理器模型产生的结果与预期结果之间的任何差异可能是由于特征硬件或与选择的操作模式相关联的特征控制电路的部分的错误。 微处理器模型可以是软件实现（即，一组指令）或硬件实现（即，逻辑设备）。

公开(公告)号：US5740183A

公开(公告)日：1998-04-14

申请号：US761005

申请日：1996-12-05

申请人： William M. Lowe

发明人： William M. Lowe

IPC分类号： G06F11/26 ,  G06F17/50 ,  G06F11/00

CPC分类号： G06F17/5022 ,  G06F11/261

摘要： Presented are a method an apparatus for operational verification of a microprocessor subject to an interrupt during a "target" activity. A software model of the microprocessor allows determination of the start and end of the target activity via one or more signals generated during the target activity. A testing program causes the microprocessor model to produce a timing signal (i.e., a trigger event) a number of system clock cycles (i.e., a delay time) before the target activity begins. A software memory model coupled to the microprocessor model includes an interrupt signal generator. The interrupt signal generator receives the trigger event and generates an interrupt signal after the delay time expires following the trigger event. A simulation trace obtained during a first "characterization" procedure is used to determine the delay time. Following the characterization procedure, the microprocessor replaces the microprocessor model. Execution of the testing program by the microprocessor causes the interrupt to occur during the target activity, and causes the microprocessor to produce a test result. The test result is compared to an expected result to determine proper operation. The microprocessor model and the memory model are contained within a memory unit of a microprocessor testing system during testing. The microprocessor testing system includes a central processing unit (CPU), chip set logic, a system bus, and a memory bus in addition to the memory unit.

摘要翻译： 提出了一种用于在“目标”活动期间受到中断的微处理器的操作验证的装置的方法。 微处理器的软件模型允许通过在目标活动期间产生的一个或多个信号确定目标活动的开始和结束。 测试程序使得微处理器模型在目标活动开始之前产生多个系统时钟周期（即，延迟时间）的定时信号（即，触发事件）。 耦合到微处理器模型的软件存储器模型包括中断信号发生器。 中断信号发生器接收触发事件，并在触发事件之后的延迟时间到期后产生中断信号。 在第一次“表征”过程中获得的模拟轨迹用于确定延迟时间。 在表征过程之后，微处理器代替微处理器模型。 微处理器执行测试程序会导致中断在目标活动期间发生，并导致微处理器产生测试结果。 将测试结果与预期结果进行比较，以确定正确的操作。 在测试期间，微处理器型号和存储器模型被包含在微处理器测试系统的存储单元内。 除了存储器单元之外，微处理器测试系统还包括中央处理单元（CPU），芯片组逻辑，系统总线和存储器总线。

公开(公告)号：US5101419A

公开(公告)日：1992-03-31

申请号：US510740

申请日：1990-04-18

申请人： William M. Lowe ,  Leland F. Rusk

发明人： William M. Lowe ,  Leland F. Rusk

IPC分类号： H03K5/156

CPC分类号： H03K5/1565

摘要： There is disclosed an improved clock generator responsive to a first clock signal having a frequency f.sub.1 and a second clock signal having a frequency f.sub.2, wherein f.sub.2 is equal to nf.sub.1. The clock generator provides a fixed duty cycle clock signal having a period equal to n complete cycles of the second clock signal and being at a first level for m complete cycles of the second clock signal and a second level for n-m complete cycles of the second clock signal. The clock generator includes a counter for counting half-cycles of the second clock signal to derive the first and second levels, and a flip-flop for establishing a timing condition responsive to the first clock signal. The clock generator further includes an inhibit circuit coupled to the counter for enabling the counter to begin a new counting period in response to the counter counting n complete cycles of the second clock signal and the establishment of the timing condition. The clock generator inhibit circuit guarantees a consistent duty cycle signal output immune to variations of the period of the first clock signal to as low as n-1/2 complete cycles of the second clock signal.

摘要翻译： 公开了一种响应于具有频率f1的第一时钟信号和具有频率f2的第二时钟信号的改进的时钟发生器，其中f2等于nf1。 时钟发生器提供具有等于第二时钟信号的n个完整周期的周期的固定占空比时钟信号，并且在第二时钟信号的m个完整周期处于第一电平，并且在第二时钟的nm个完整周期 信号。 时钟发生器包括用于计数第二时钟信号的半周期以计算第一和第二电平的计数器，以及用于响应于第一时钟信号建立定时条件的触发器。 时钟发生器还包括耦合到计数器的禁止电路，用于使计数器响应于计数器计数第二时钟信号的n个完整周期和建立定时条件而开始新的计数周期。 时钟发生器禁止电路保证一致的占空比信号输出免受第一时钟信号周期的变化，低至第二时钟信号的n-1/2个完整周期。