公开(公告)号：US07927932B2

公开(公告)日：2011-04-19

申请号：US12923471

申请日：2010-09-23

Applicant: Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

Inventor： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC: H01L21/84

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

Abstract translation: 根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。 半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。 源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。 非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。 金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。 绝缘间隔物可以设置在金属字线的侧壁上。 金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。 示例性实施例还涉及制造上述半导体器件的方法。

公开(公告)号：US20110014754A1

公开(公告)日：2011-01-20

申请号：US12923471

申请日：2010-09-23

Applicant: Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

Inventor： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC: H01L21/8234

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

公开(公告)号：US07671389B2

公开(公告)日：2010-03-02

申请号：US11385473

申请日：2006-03-21

Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC: H01L31/112

CPC classification number: H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

Abstract translation: SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US07589992B2

公开(公告)日：2009-09-15

申请号：US11953289

申请日：2007-12-10

Applicant: Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

Inventor： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

Abstract: A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

Abstract translation: 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US20090224330A1

公开(公告)日：2009-09-10

申请号：US12468415

申请日：2009-05-19

Applicant: Chang Min Hong ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Kun-Ho Kwak ,  Byoung-Keun Son ,  Jong-Hoon Na ,  Yeon-Wook Jung ,  Ju-Young Lim

Inventor： Chang Min Hong ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Kun-Ho Kwak ,  Byoung-Keun Son ,  Jong-Hoon Na ,  Yeon-Wook Jung ,  Ju-Young Lim

IPC: H01L27/11 ,  H01L25/065 ,  H01L21/30

CPC classification number: G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

Abstract: A semiconductor memory device and method of manufacturing the same are disclosed. The semiconductor memory device includes a semiconductor substrate having a cell region and a peripheral circuit region, first transistors provided on the semiconductor substrate, a first semiconductor layer provided on the first transistors, and bonded by a bonding technique, and second transistors provided on the first semiconductor layer, wherein the first and second transistors are provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer, respectively, and a metal layer is formed on gates of the first and second transistors respectively provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer. As a result, the transistors in the peripheral circuit region requiring high performance can be formed on an upper layer and a lower layer.

Abstract translation: 公开了一种半导体存储器件及其制造方法。 半导体存储器件包括具有单元区域和外围电路区域的半导体衬底，设置在半导体衬底上的第一晶体管，设置在第一晶体管上的第一半导体层，并通过接合技术接合，第二晶体管设置在第一晶体管上 半导体层，其中第一和第二晶体管分别设置在半导体衬底和第一半导体层的外围电路区域中，并且在分别设置在半导体衬底的外围电路区域中的第一和第二晶体管的栅极上形成金属层 半导体衬底和第一半导体层。 结果，可以在上层和下层上形成需要高性能的外围电路区域中的晶体管。

公开(公告)号：US20090185407A1

公开(公告)日：2009-07-23

申请号：US12408932

申请日：2009-03-23

Applicant: Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

Inventor： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC: G11C5/02 ,  G11C8/08 ,  G11C11/00 ,  G11C5/06

CPC classification number: G11C11/412 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/08 ,  G11C8/12 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

Abstract: Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers.

Abstract translation: 提供了具有堆叠结构的晶体管的半导体器件。 具有晶体管的半导体存储器件包括存储单元阵列块，其包括多个字线和多个存储单元，每个存储单元包括连接在多个字线之间的至少一个第一晶体管，以及包括多个字线的字线解码器 分别驱动多个字线的驱动器，其中多个字线被布置在第一层上，并且多个驱动器设置在至少两个第二层上。

公开(公告)号：US20060216886A1

公开(公告)日：2006-09-28

申请号：US11385473

申请日：2006-03-21

Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

Abstract translation: SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US20090294863A1

公开(公告)日：2009-12-03

申请号：US12537521

申请日：2009-08-07

Applicant: Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

Inventor： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC: H01L29/66

CPC classification number: G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

Abstract: A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

Abstract translation: 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US07589375B2

公开(公告)日：2009-09-15

申请号：US11642297

申请日：2006-12-20

Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

IPC: H01L27/115

CPC classification number: H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

Abstract: A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

Abstract translation: 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

公开(公告)号：US07315466B2

公开(公告)日：2008-01-01

申请号：US11191496

申请日：2005-07-28

Applicant: Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

Inventor： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

Abstract: A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

Abstract translation: 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。