公开(公告)号：US20050285768A1

公开(公告)日：2005-12-29

申请号：US11157923

申请日：2005-06-22

申请人： Hiroyuki Hagiwara ,  Haruo Kobayashi ,  Hao San ,  Atsushi Wada

发明人： Hiroyuki Hagiwara ,  Haruo Kobayashi ,  Hao San ,  Atsushi Wada

IPC分类号： H03M1/06 ,  H03M1/66 ,  H03M1/80 ,  H03M3/00 ,  H03M3/04

CPC分类号： H03M1/0665 ,  H03M1/806 ,  H03M3/43 ,  H03M3/464

摘要： A DA converter circuit is provided for use in a ΔΣ AD modulator. The DA converter circuit includes a DA converter of segment switched capacitor type. The DA converter includes an operational amplifier, capacitors as connected in parallel to each other to supply electric charges to the operational amplifier, an electrically charging switch for switching of electrically charging electric charges onto the respective capacitors or not, and an electrically discharging switch for switching or not electrically discharging electric charges from the respective capacitors or not. A switch device performs either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors. A controller controls the electrically charging switch, the electrically discharging switch and the switch device to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit.

摘要翻译： 提供了用于DeltaSigma AD调制器的DA转换器电路。 DA转换器电路包括段转换电容器类型的DA转换器。 DA转换器包括运算放大器，彼此并联连接的电容器，以向运算放大器提供电荷，用于将充电电荷转换到各个电容器上的充电开关，以及用于切换的放电开关 或不从各个电容器中电荷放电。 开关装置对各个电容器进行充电，放电，接地和极性反转之一。 控制器控制充电开关，放电开关和开关装置，以执行用于执行DA转换器电路的非线性的二阶噪声整形的二阶DWA算法的处理。

公开(公告)号：US07095350B2

公开(公告)日：2006-08-22

申请号：US11157923

申请日：2005-06-22

申请人： Hiroyuki Hagiwara ,  Haruo Kobayashi ,  Hao San ,  Atsushi Wada

发明人： Hiroyuki Hagiwara ,  Haruo Kobayashi ,  Hao San ,  Atsushi Wada

IPC分类号： H03M1/66 ,  H03M3/00

CPC分类号： H03M1/0665 ,  H03M1/806 ,  H03M3/43 ,  H03M3/464

摘要： A DA converter circuit is provided for use in a ΔΣ AD modulator. The DA converter circuit includes a DA converter of segment switched capacitor type. The DA converter includes an operational amplifier, capacitors as connected in parallel to each other to supply electric charges to the operational amplifier, an electrically charging switch for switching of electrically charging electric charges onto the respective capacitors or not, and an electrically discharging switch for switching or not electrically discharging electric charges from the respective capacitors or not. A switch device performs either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors. A controller controls the electrically charging switch, the electrically discharging switch and the switch device to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit.

摘要翻译： 提供了用于DeltaSigma AD调制器的DA转换器电路。 DA转换器电路包括段转换电容器类型的DA转换器。 DA转换器包括运算放大器，彼此并联连接的电容器，以向运算放大器提供电荷，用于将充电电荷转换到各个电容器上的充电开关，以及用于切换的放电开关 或不从各个电容器中电荷放电。 开关装置对各个电容器进行充电，放电，接地和极性反转之一。 控制器控制充电开关，放电开关和开关装置，以执行用于执行DA转换器电路的非线性的二阶噪声整形的二阶DWA算法的处理。

公开(公告)号：US07629911B2

公开(公告)日：2009-12-08

申请号：US12096021

申请日：2006-08-01

申请人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

发明人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

IPC分类号： H03M3/00

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/338 ,  H03M3/424 ,  H03M3/464

摘要： A high-precision ΔΣ modulator reduces nonlinear noise due to the use of a multibit DAC and has little hardware and power consumption. A digital signal is DA converted and fed back to a subtraction circuit supplied with an analog signal. The DAC used in this feedback circuit uses a DAC (DWADAC) that includes a weighted pointer so that input digital signals are supplied in order to a plurality of segment elements that construct the DAC. In this DWADAC, the construction and number of the pointer is set based on the type and order of the filter disposed before the ADC.

摘要翻译： 高精度DeltaSigma调制器由于使用多位DAC而降低了非线性噪声，几乎没有硬件和功耗。 数字信号被DA转换并反馈到提供有模拟信号的减法电路。 在该反馈电路中使用的DAC使用包括加权指针的DAC（DWADAC），以便为构成DAC的多个段元件提供输入数字信号。 在这个DWADAC中，指针的构造和数量是根据ADC之前设置的滤波器的类型和顺序设置的。

公开(公告)号：US20060284751A1

公开(公告)日：2006-12-21

申请号：US11408941

申请日：2006-04-24

申请人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

发明人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

IPC分类号： H03M3/00

CPC分类号： H03M3/34 ,  H03M3/40 ,  H03M3/402 ,  H03M3/424 ,  H03M3/454

摘要： In a first-order complex band-pass filter, multiplexers are alternately switched over between time intervals of phases A and B, where the multiplexers includes two multiplexers provided at input and output stages, and a multiplexer provided in a feedback circuit of each of first-order filters and being switching over whether to invert a sign of a feedback signal. Then in a circuit part sandwiched between the multiplexers, a processing performed by an I circuit part and a processing performed by a Q circuit part are alternately switched over so that a sign of a signal inputted to an adder is inverted.

摘要翻译： 在一阶复数带通滤波器中，多路复用器在相位A和B的时间间隔之间交替切换，其中多路复用器包括在输入和输出级提供的两个多路复用器，以及多路复用器，其设置在第一 - 顺序滤波器并切换是否反转反馈信号的符号。 然后在夹在多路复用器之间的电路部分中，交替地切换由I电路部分执行的处理和由Q电路部分执行的处理，使得输入到加法器的信号的符号反转。

公开(公告)号：US20090167581A1

公开(公告)日：2009-07-02

申请号：US12096021

申请日：2006-08-01

申请人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

发明人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

IPC分类号： H03M3/00

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/338 ,  H03M3/424 ,  H03M3/464

摘要： A high-precision ΔΣ modulator reduces nonlinear noise due to the use of a multibit DAC and has little hardware and power consumption. A digital signal is DA converted and fed back to a subtraction circuit supplied with an analog signal. The DAC used in this feedback circuit uses a DAC (DWADAC) that includes a weighted pointer so that input digital signals are supplied in order to a plurality of segment elements that construct the DAC. In this DWADAC, the construction and number of the pointer is set based on the type and order of the filter disposed before the ADC.

摘要翻译： 高精度DeltaSigma调制器由于使用多位DAC而降低了非线性噪声，几乎没有硬件和功耗。 数字信号被DA转换并反馈到提供有模拟信号的减法电路。 在该反馈电路中使用的DAC使用包括加权指针的DAC（DWADAC），以便为构成DAC的多个段元件提供输入数字信号。 在这个DWADAC中，指针的构造和数量是根据ADC之前设置的滤波器的类型和顺序设置的。

公开(公告)号：US07227482B2

公开(公告)日：2007-06-05

申请号：US11408941

申请日：2006-04-24

申请人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

发明人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

IPC分类号： H03M3/00

CPC分类号： H03M3/34 ,  H03M3/40 ,  H03M3/402 ,  H03M3/424 ,  H03M3/454

摘要： In a first-order complex band-pass filter, multiplexers are alternately switched over between time intervals of phases A and B, where the multiplexers includes two multiplexers provided at input and output stages, and a multiplexer provided in a feedback circuit of each of first-order filters and being switching over whether to invert a sign of a feedback signal. Then in a circuit part sandwiched between the multiplexers, a processing performed by an I circuit part and a processing performed by a Q circuit part are alternately switched over so that a sign of a signal inputted to an adder is inverted.

摘要翻译： 在一阶复数带通滤波器中，多路复用器在相位A和B的时间间隔之间交替切换，其中多路复用器包括在输入和输出级提供的两个多路复用器，以及多路复用器，其设置在第一 - 顺序滤波器并切换是否反转反馈信号的符号。 然后在夹在多路复用器之间的电路部分中，交替地切换由I电路部分执行的处理和由Q电路部分执行的处理，使得输入到加法器的信号的符号反转。

公开(公告)号：US07098828B2

公开(公告)日：2006-08-29

申请号：US11157848

申请日：2005-06-22

申请人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

发明人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

IPC分类号： H03M3/00 ,  H03M1/00 ,  H04B14/06

CPC分类号： H03M3/34 ,  H03M1/0665 ,  H03M3/40 ,  H03M3/424 ,  H03M3/464

摘要： A complex band-pass ΔΣ AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.

摘要翻译： 复数带通DeltaSigma AD调制器具有减法器件，复带通滤波器，第一和第二AD转换器以及第一和第二DA转换器。 第一和第二DA转换器和第一和第二逻辑电路夹在第一和第二多路复用器之间。 在时钟信号的第一定时，第一多路复用器原样输入并输出第一和第二数字信号，并且在其第二定时，第一多路复用器输入第一和第二数字信号，并将第一数字信号作为 第二数字信号并输出​​第二数字信号作为第一数字信号。 第二多路复用器类似地输入和输出第一和第二模拟信号。 通过使用高通和低通元素旋转方法实现复杂的数字和模拟滤波器，第一和第二逻辑电路基本上噪声地形成第一和第二DA转换器的非线性。

公开(公告)号：US20050285766A1

公开(公告)日：2005-12-29

申请号：US11157848

申请日：2005-06-22

申请人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

发明人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

IPC分类号： H03M1/06 ,  H03M3/00 ,  H03M3/04

CPC分类号： H03M3/34 ,  H03M1/0665 ,  H03M3/40 ,  H03M3/424 ,  H03M3/464

摘要： A complex band-pass ΔΣ AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.

摘要翻译： 复数带通DeltaSigma AD调制器具有减法器件，复带通滤波器，第一和第二AD转换器以及第一和第二DA转换器。 第一和第二DA转换器和第一和第二逻辑电路夹在第一和第二多路复用器之间。 在时钟信号的第一定时，第一多路复用器原样输入并输出第一和第二数字信号，并且在其第二定时，第一多路复用器输入第一和第二数字信号，并将第一数字信号作为 第二数字信号并输出​​第二数字信号作为第一数字信号。 第二多路复用器类似地输入和输出第一和第二模拟信号。 通过使用高通和低通元素旋转方法实现复杂的数字和模拟滤波器，第一和第二逻辑电路基本上噪声地形成第一和第二DA转换器的非线性。

公开(公告)号：US08436757B2

公开(公告)日：2013-05-07

申请号：US13254333

申请日：2010-02-24

申请人： Hao San ,  Haruo Kobayashi

发明人： Hao San ,  Haruo Kobayashi

IPC分类号： H03M3/00

CPC分类号： H03M3/368 ,  H03M3/40

摘要： To provide a complex bandpass ΔΣAD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption.A complex bandpass ΔΣAD modulator 10 is configured by a subtraction unit 20, a complex bandpass filter 30, an addition unit 40, a noise extraction circuit unit 50, an ADC unit 60, and a DAC unit 70. The noise extraction circuit unit 50 extracts a quantized noise signal of the ADC unit 60 based on an input signal of the ADC unit 60 and an output signal of the DAC unit 70, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit 60. Thus, a complex bandpass ΔΣAD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.

摘要翻译： 提供一种复杂的带通DeltaSigmaAD调制器，其能够抑制由I信道和Q信道之间的失配引起的图像分量对具有低功耗的信号分量的影响。 复数带通DeltaSigmaAD调制器10由减法单元20，复带通滤波器30，加法单元40，噪声提取电路单元50，ADC单元60和DAC单元70构成。噪声提取电路单元50提取 基于ADC单元60的输入信号和DAC单元70的输出信号的ADC单元60的量化噪声信号将所提取的量化噪声信号延迟一个采样时间，将延迟信号相位旋转预定角度 ，并将旋转的信号反馈到ADC单元60的输入侧。因此，能够抑制由I信道和Q信道之间的失配引起的图像分量对信号分量的影响的复数带通DeltaSigmaAD调制器 提供功耗。

公开(公告)号：US20110316729A1

公开(公告)日：2011-12-29

申请号：US13254333

申请日：2010-02-24

申请人： Hao San ,  Haruo Kobayashi

发明人： Hao San ,  Haruo Kobayashi

IPC分类号： H03M3/02

CPC分类号： H03M3/368 ,  H03M3/40

摘要： To provide a complex bandpass ΔΣAD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption.A complex bandpass READ modulator 10 is configured by a subtraction unit 20, a complex bandpass filter 30, an addition unit 40, a noise extraction circuit unit 50, an ADC unit 60, and a DAC unit 70. The noise extraction circuit unit 50 extracts a quantized noise signal of the ADC unit 60 based on an input signal of the ADC unit 60 and an output signal of the DAC unit 70, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit 60. Thus, a complex bandpass ΔΣAD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.

摘要翻译： 提供一种复杂的带通＆Dgr＆amp; AD调制器，其能够抑制由于具有低功耗的信号分量上的I通道和Q通道之间的失配引起的图像分量的影响。 复数带通读调制器10由减法单元20，复带通滤波器30，加法单元40，噪声提取电路单元50，ADC单元60和DAC单元70构成。噪声提取电路单元50提取 基于ADC单元60的输入信号和DAC单元70的输出信号的ADC单元60的量化噪声信号将所提取的量化噪声信号延迟一个采样时间，将延迟信号相位旋转预定角度 ，并将旋转的信号反馈到ADC单元60的输入侧。因此，能够抑制由I和Q通道之间的失配引起的图像分量对该影像分量的影响的复数带通＆Dgr＆amp; 提供低功耗的信号分量。