公开(公告)号：US08368158B2

公开(公告)日：2013-02-05

申请号：US12758646

申请日：2010-04-12

Applicant: In-Gyun Jeon ,  Se-Jung Oh ,  Heui-Gyun Ahn ,  Jun-Ho Won

Inventor： In-Gyun Jeon ,  Se-Jung Oh ,  Heui-Gyun Ahn ,  Jun-Ho Won

IPC: H01L31/0232

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract translation: 具有波导的图像传感器包括形成有光电二极管和外围电路区域的半导体基板; 形成在半导体衬底上的抗反射层; 形成在所述抗反射层上的绝缘层; 形成在所述绝缘层上并连接到所述半导体衬底的布线层; 堆叠在所述布线层上的至少一层间电介质; 以及通过穿过形成在光电二极管上的层间电介质和布线层与绝缘层连接的波导。

公开(公告)号：US20120301996A1

公开(公告)日：2012-11-29

申请号：US13563655

申请日：2012-07-31

Applicant: In-Gyun Jeon ,  Se-Jung Oh ,  Heui-Gyun Ahn ,  Jun-Ho Won

Inventor： In-Gyun Jeon ,  Se-Jung Oh ,  Heui-Gyun Ahn ,  Jun-Ho Won

IPC: H01L31/18

CPC classification number: H01L27/1464 ,  H01L27/14634

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract translation: 减小芯片尺寸的背面照明图像传感器具有设置在后侧照明图像传感器中的像素区域的垂直上部的电容器，其中光从用户的背面被照射，从而减小了芯片尺寸，并且 背面照明图像传感器的制造方法。 减少芯片尺寸的背面照明图像传感器的电容器形成在像素区域的垂直上部，而不是在像素区域的外侧，使得不需要用于形成电容器的像素区域的外部区域 ，从而减小芯片尺寸。

公开(公告)号：US20120295389A1

公开(公告)日：2012-11-22

申请号：US13563620

申请日：2012-07-31

Applicant: In-Gyun JEON ,  Se-Jung OH ,  Heui-Gyun AHN ,  Jun-Ho WON

Inventor： In-Gyun JEON ,  Se-Jung OH ,  Heui-Gyun AHN ,  Jun-Ho WON

IPC: H01L31/0232

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract translation: 具有波导的图像传感器包括形成有光电二极管和外围电路区域的半导体基板; 形成在半导体衬底上的抗反射层; 形成在所述抗反射层上的绝缘层; 形成在所述绝缘层上并连接到所述半导体衬底的布线层; 堆叠在所述布线层上的至少一层间电介质; 以及通过穿过形成在光电二极管上的层间电介质和布线层与绝缘层连接的波导。

公开(公告)号：US07772666B2

公开(公告)日：2010-08-10

申请号：US11616047

申请日：2006-12-26

Applicant: Heui Gyun Ahn

Inventor： Heui Gyun Ahn

IPC: H01L31/058

CPC classification number: H01L27/14643 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14689

Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor may be capable of improved thickness uniformity form microlenses formed at a reduced distance from the photodiodes. The CMOS image sensor can include: a semiconductor substrate on which a pixel array is formed, the pixel array including photodiodes formed on the semiconductor substrate to different depths for sensing red, green, and blue signals, respectively; an interlayer dielectric formed on the semiconductor substrate and having a trench at an upper portion of the pixel array; an insulating layer sidewall formed at a side of the trench; and a plurality of microlenses formed on the interlayer dielectric in the trench at predetermined intervals.

Abstract translation: 提供CMOS图像传感器及其制造方法。 CMOS图像传感器可以具有改善的厚度均匀性，形成在与光电二极管相距减小的距离处形成的微透镜。 CMOS图像传感器可以包括：其上形成有像素阵列的半导体衬底，所述像素阵列包括形成在所述半导体衬底上的不同深度的用于感测红色，绿色和蓝色信号的不同深度的光电二极管; 形成在所述半导体衬底上并且在所述像素阵列的上部具有沟槽的层间电介质; 形成在所述沟槽的一侧的绝缘层侧壁; 以及以规定间隔形成在沟槽中的层间电介质上的多个微透镜。

公开(公告)号：US08816459B2

公开(公告)日：2014-08-26

申请号：US13563620

申请日：2012-07-31

Applicant: In-Gyun Jeon ,  Se-Jung Oh ,  Heui-Gyun Ahn ,  Jun-Ho Won

Inventor： In-Gyun Jeon ,  Se-Jung Oh ,  Heui-Gyun Ahn ,  Jun-Ho Won

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract translation: 具有波导的图像传感器包括形成有光电二极管和外围电路区域的半导体基板; 形成在半导体衬底上的抗反射层; 形成在所述抗反射层上的绝缘层; 形成在所述绝缘层上并连接到所述半导体衬底的布线层; 堆叠在所述布线层上的至少一层间电介质; 以及通过穿过形成在光电二极管上的层间电介质和布线层与绝缘层连接的波导。

公开(公告)号：US08420429B2

公开(公告)日：2013-04-16

申请号：US13563655

申请日：2012-07-31

Applicant: In Gyun Jeon ,  Se Jung Oh ,  Heui Gyun Ahn ,  Jun Ho Won

Inventor： In Gyun Jeon ,  Se Jung Oh ,  Heui Gyun Ahn ,  Jun Ho Won

IPC: H01L21/00

CPC classification number: H01L27/1464 ,  H01L27/14634

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

公开(公告)号：US08399282B2

公开(公告)日：2013-03-19

申请号：US13026963

申请日：2011-02-14

Applicant: Heui Gyun Ahn ,  Se Jung Oh ,  In Gyun Jeon ,  Jun Ho Won

Inventor： Heui Gyun Ahn ,  Se Jung Oh ,  In Gyun Jeon ,  Jun Ho Won

IPC: H01L21/00

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/68372 ,  H01L2224/05093 ,  H01L2924/01046 ,  H01L2924/01078

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.

Abstract translation: 公开了一种用于在具有三维堆叠结构的晶片中形成焊盘的方法。 该方法包括将包括Si衬底和处理晶片的器件晶片接合，使Si衬底的背面变薄，在Si衬底的减薄的背侧上沉积抗反射层，在其上沉积背面电介质层 抗反射层，形成穿过抗反射层和背面电介质层的通孔，并接触形成在Si衬底上的超级触点的背面，并在背面电介质层上形成焊盘，使得焊盘 电连接到通孔。

公开(公告)号：US20070152286A1

公开(公告)日：2007-07-05

申请号：US11616047

申请日：2006-12-26

Applicant: Heui Gyun Ahn

Inventor： Heui Gyun Ahn

IPC: H01L29/82

CPC classification number: H01L27/14643 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14689

Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor may be capable of improved thickness uniformity form microlenses formed at a reduced distance from the photodiodes. The CMOS image sensor can include: a semiconductor substrate on which a pixel array is formed, the pixel array including photodiodes formed on the semiconductor substrate to different depths for sensing red, green, and blue signals, respectively; an interlayer dielectric formed on the semiconductor substrate and having a trench at an upper portion of the pixel array; an insulating layer sidewall formed at a side of the trench; and a plurality of microlenses formed on the interlayer dielectric in the trench at predetermined intervals.

Abstract translation: 提供CMOS图像传感器及其制造方法。 CMOS图像传感器可以具有改善的厚度均匀性，形成在与光电二极管相距减小的距离处形成的微透镜。 CMOS图像传感器可以包括：其上形成有像素阵列的半导体衬底，所述像素阵列包括形成在所述半导体衬底上的不同深度的用于感测红色，绿色和蓝色信号的不同深度的光电二极管; 形成在所述半导体衬底上并且在所述像素阵列的上部具有沟槽的层间电介质; 形成在所述沟槽的一侧的绝缘层侧壁; 以及以规定间隔形成在沟槽中的层间电介质上的多个微透镜。

公开(公告)号：US20070077723A1

公开(公告)日：2007-04-05

申请号：US11320725

申请日：2005-12-30

Applicant: Heui-Gyun Ahn

Inventor： Heui-Gyun Ahn

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: An exemplary method of forming a shallow trench isolation layer in a semiconductor device according to an embodiment of the present invention includes depositing a silicon nitride layer as a hard mask layer on a silicon substrate, forming a first moat pattern in the silicon nitride layer by a photolithography process, patterning the silicon nitride layer by a dry etching process using the first moat pattern as an etching mask, forming a shallow trench by dry-etching the substrate that is exposed by the patterned silicon nitride layer, removing the first moat pattern after forming the shallow trench, removing the patterned silicon nitride layer, filling the shallow trench with a gap-fill insulation layer, forming a second moat pattern, removing the gap-fill insulation layer by a dry etching process using the second moat pattern as an etching mask, and removing the second moat pattern.

Abstract translation: 根据本发明的实施例的在半导体器件中形成浅沟槽隔离层的示例性方法包括在硅衬底上沉积氮化硅层作为硬掩模层，在氮化硅层中形成第一沟槽图案 光刻工艺，通过使用第一护套图案作为蚀刻掩模的干蚀刻工艺对氮化硅层进行图案化，通过干蚀刻由图案化的氮化硅层曝光的衬底形成浅沟槽，在形成之后去除第一沟槽图案 浅沟槽，去除图案化的氮化硅层，用间隙填充绝缘层填充浅沟槽，形成第二沟槽图案，通过使用第二沟槽图案作为蚀刻掩模的干蚀刻工艺去除间隙填充绝缘层 ，并且移除第二护城河图案。

公开(公告)号：US08421134B2

公开(公告)日：2013-04-16

申请号：US12976851

申请日：2010-12-22

Applicant: In Gyun Jeon ,  Se Jung Oh ,  Heui Gyun Ahn ,  Jun Ho Won

Inventor： In Gyun Jeon ,  Se Jung Oh ,  Heui Gyun Ahn ,  Jun Ho Won

IPC: H01L31/18

CPC classification number: H01L27/1464 ,  H01L27/14634

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract translation: 减小芯片尺寸的背面照明图像传感器具有设置在后侧照明图像传感器中的像素区域的垂直上部的电容器，其中光从用户的背面被照射，从而减小了芯片尺寸，并且 背面照明图像传感器的制造方法。 减少芯片尺寸的背面照明图像传感器的电容器形成在像素区域的垂直上部，而不是在像素区域的外侧，使得不需要用于形成电容器的像素区域的外部区域 ，从而减小芯片尺寸。