利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.017 秒)

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5440521A

    公开(公告)日：1995-08-08

    申请号：US109071

    申请日：1993-08-19

    申请人： Manabu Tsunozaki ,  Kyoko Ishii ,  Koichi Nozaki ,  Hiroshi Yoshioka ,  Yoshihisa Koyama ,  Shinji Udo ,  Hidetomo Aoyagi ,  Sinichi Miyatake ,  Makoto Morino ,  Akihiko Hoshida

    发明人： Manabu Tsunozaki ,  Kyoko Ishii ,  Koichi Nozaki ,  Hiroshi Yoshioka ,  Yoshihisa Koyama ,  Shinji Udo ,  Hidetomo Aoyagi ,  Sinichi Miyatake ,  Makoto Morino ,  Akihiko Hoshida

    IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L27/108 ,  H01L27/10

    CPC分类号： H01L27/10805 ,  G11C5/025

    摘要： A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat. At least some of wiring lines connected to each sense amplifier are formed in a wiring layer in which Y-selection lines are formed. The Y-selection lines are extended in gaps between the sense amplifiers.

    摘要翻译： 一种半导体集成电路器件，由多个组合构成，每组具有一对存储器阵列，每个存储器阵列具有以矩阵形式排列的多个存储单元，以及一个读出放大器，用于发送由该感测器提供的信号的I / O线 放大器，用于选择用于发送由I / O线上的读出放大器提供的信号的条件的选择电路或用于在I / O线上不发送其的条件，以及用于发送选择的Y选择线 信号。 连接有选择的解码器基本上设置在Y选择线的中间。 X和Y地址缓冲器被布置成比X和Y冗余电路更靠近芯片的中心。 参考电压产生电路设置成比输出缓冲电路更靠近芯片的边缘。 每个存储器垫的浮雕选择电路与包括在同一存储器垫中的冗余线选择电路相邻地形成。 连接到每个读出放大器的至少一些布线形成在其中形成Y选择线的布线层中。 Y选择线在读出放大器之间的间隙中扩展。

    Semiconductor memory system
    5.
    发明授权
    Semiconductor memory system 失效
    半导体存储器系统

    公开(公告)号：US5598373A

    公开(公告)日：1997-01-28

    申请号：US476765

    申请日：1995-06-07

    申请人： Shoji Wada ,  Kanehide Kenmizaki ,  Masaya Muranaka ,  Masahiro Ogata ,  Hidetomo Aoyagi ,  Tetsuya Kitame ,  Masahiro Katayama ,  Shoji Kubono ,  Yukihide Suzuki ,  Makoto Morino ,  Sinichi Miyatake ,  Seiichi Shundo ,  Yoshihisa Koyama ,  Nobuhiko Ohno

    发明人： Shoji Wada ,  Kanehide Kenmizaki ,  Masaya Muranaka ,  Masahiro Ogata ,  Hidetomo Aoyagi ,  Tetsuya Kitame ,  Masahiro Katayama ,  Shoji Kubono ,  Yukihide Suzuki ,  Makoto Morino ,  Sinichi Miyatake ,  Seiichi Shundo ,  Yoshihisa Koyama ,  Nobuhiko Ohno

    IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  H01L21/82 ,  G11C7/00 ,  G11C8/00 ,  G11C11/34

    CPC分类号： G11C29/80 ,  G11C29/02 ,  G11C29/44

    摘要： A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.

    摘要翻译： 安装在存储器模块上的缺陷补救LSI包括：用于捕获地址和控制信号的输入接口部分，所述输入接口部分与动态RAM的相同; 对应于由多个动态随机存取存储器构成的存储器件的数据总线的输入/输出接口部分; 存储器电路，其中电子地写入多个随机存取存储器中的任何一个的芯片地址和X缺陷地址，所述存储器电路基本上是非易失性的; 由静态RAM组成的冗余补救RAM部分，其中通过X地址信号和存储器电路的缺陷地址之间的比较匹配信号来选择字线，X地址信号和缺陷地址经由输入接口部分捕获 并且通过经由输入接口部分捕获的Y地址信号来选择列; 选择部分，用于将冗余补救RAM部分的数据输入/输出总线连接到对应于有缺陷的芯片地址的输入/输出电路; 数据输入/输出部分，用于选择性地激活要连接到与发现有缺陷的动态RAM相对应的数据总线的输入/输出电路; 以及掩模部分，用于在读取操作中输出用于将缺陷RAM的输出引脚置于高阻抗状态的控制信号。