公开(公告)号：US06990623B2

公开(公告)日：2006-01-24

申请号：US10146074

申请日：2002-05-16

申请人： Hideyuki Furukawa

发明人： Hideyuki Furukawa

IPC分类号： G11C29/00

CPC分类号： H03M13/11 ,  G06F11/1072 ,  G11C11/56

摘要： Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of data corresponding to all the binary bit addresses having “0” in the digit and a parity code of data corresponding to all the binary bit addresses having “1” in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.

公开(公告)号：US06937526B2

公开(公告)日：2005-08-30

申请号：US10634757

申请日：2003-08-06

申请人： Hideyuki Furukawa

发明人： Hideyuki Furukawa

IPC分类号： G06F12/16 ,  G06F3/06 ,  G06F3/08 ,  G06K17/00 ,  G06K19/07 ,  G11C29/48 ,  G11C16/04

CPC分类号： G11C29/48

摘要： In a memory card which includes a memory chip and a controller connected to the memory chip for the control of transferring a data from outside, the controller is provided with a buffer in which data is temporarily stored. In a first operation mode, the controller clears the data stored in the buffer after the data in the buffer is transferred to the memory chip. In a second operation mode, the controller does not clear the data stored in the buffer even after the data in the buffer is transferred to the memory chip. By the use of these modes, it becomes possible to write the data obtained by means of external transfer into the memory chip repeatedly for a plurality of times by means of internal transfer. Thus, it becomes unnecessary to repeat external transfer and internal transfer every time.

摘要翻译： 在包括存储器芯片的存储卡和连接到存储器芯片的用于控制从外部传送数据的控制器的控制器中设置有暂时存储数据的缓冲器。 在第一操作模式中，在将缓冲器中的数据传送到存储器芯片之后，控制器清除存储在缓冲器中的数据。 在第二操作模式中，即使在将缓冲器中的数据传送到存储器芯片之后，控制器也不清除存储在缓冲器中的数据。 通过使用这些模式，可以通过内部传送将通过外部传送获得的数据反复写入存储器芯片多次。 因此，不必每次重复外部转移和内部转移。

公开(公告)号：US06862672B1

公开(公告)日：2005-03-01

申请号：US09583233

申请日：2000-05-31

申请人： Tomomi Furudate ,  Takaaki Ichikawa ,  Junya Kawamata ,  Hideyuki Furukawa ,  Haruo Shoji ,  Yuzuru Matsuno ,  Tatsuya Yoshimoto ,  Masato Kitamura

发明人： Tomomi Furudate ,  Takaaki Ichikawa ,  Junya Kawamata ,  Hideyuki Furukawa ,  Haruo Shoji ,  Yuzuru Matsuno ,  Tatsuya Yoshimoto ,  Masato Kitamura

IPC分类号： G11C11/41 ,  G06F12/00 ,  G11C8/20 ,  G11C16/06 ,  G11C16/22

CPC分类号： G11C8/20 ,  G11C16/22

摘要： A plurality of memory cells corresponding to an address space larger than 2n and smaller than 2(n+1), an invalid address detecting circuit, and an invalid signal outputting circuit are comprised. Upon command input, the invalid address detecting circuit invalidates a command in the case where the invalid address detecting circuit detects a fact that an address signal supplied from exterior indicates an invalid address space. Therefore, at the time of invalid address supply, internal circuits are not activated and an erroneous write or erase operation can be prevented. Since the internal circuits do not operate, power consumption can be reduced substantially. The invalid signal outputting circuit outputs an invalid signal by receiving the fact of invalid address signal detection by the invalid address detecting circuit. Therefore, a system unit mounting the semiconductor memory device can easily recognize that the invalid address signal has been supplied to the semiconductor memory device. As a result, a malfunctioning can be prevented and reliability of the system unit improves.

摘要翻译： 包括对应于大于2 且小于2 <（n + 1）>的地址空间的多个存储单元，无效地址检测电路和无效信号输出电路。 在命令输入时，无效地址检测电路在无效地址检测电路检测到从外部提供的地址信号表示无效地址空间的事实的情况下使命令无效。 因此，在无效地址提供时，内部电路不被激活，并且可以防止错误的写入或擦除操作。 由于内部电路不工作，所以能够大幅度降低功耗。 无效信号输出电路通过接收无效地址检测电路的无效地址信号检测的事实来输出无效信号。 因此，安装半导体存储器件的系统单元可以容易地识别出无效地址信号已被提供给半导体存储器件。 结果，可以防止故障，并且系统单元的可靠性提高。

公开(公告)号：US06631276B1

公开(公告)日：2003-10-07

申请号：US09644552

申请日：2000-08-24

申请人： Takashi Yamaguchi ,  Hideyuki Furukawa ,  Osamu Nakashima ,  Naoki Koga

发明人： Takashi Yamaguchi ,  Hideyuki Furukawa ,  Osamu Nakashima ,  Naoki Koga

IPC分类号： H04B138

CPC分类号： H01Q1/088 ,  H01Q1/241 ,  H01Q1/244

摘要： A base unit accommodates a radio terminal for making radio communications. This base unit has a recess for accommodating part of the radio terminal formed at least in two mutually orthogonal planes of the base unit body. An opening is formed at the inner side of the recess. Inside the base unit, a connector electrically connects and fixes the radio terminal. A rear part of the radio terminal is inserted through the opening. The base unit includes a lid for shielding the entire recess. The base unit body may include an external antenna connected to a cable having a terminal for connecting with an external antenna terminal provided in the radio terminal. This terminal may be disposed at a position corresponding to the external antenna terminal of the radio terminal of the lid. The base unit design is improved, invasion of foreign matter is prevented, and the radio reaching distance and directivity of the base unit are enhanced.

摘要翻译： 基地单元容纳用于进行无线电通信的无线电终端。 该基座单元具有用于容纳形成在基座单元主体的至少两个相互正交的平面中的无线电终端的部分的凹部。 在凹部的内侧形成开口。 在基座单元内，连接器电连接并固定无线电终端。 无线电终端的后部通过开口插入。 基座单元包括用于屏蔽整个凹部的盖子。 基座单元主体可以包括连接到具有用于与设置在无线终端中的外部天线端子连接的终端的电缆的外部天线。 该终端可以设置在与盖的无线终端的外部天线端子对应的位置。 改进了基本单元设计，防止异物入侵，提高了基站的无线电达到距离和方向性。

公开(公告)号：US06957377B2

公开(公告)日：2005-10-18

申请号：US09911375

申请日：2001-07-25

申请人： Hideyuki Furukawa

发明人： Hideyuki Furukawa

IPC分类号： G06F12/16 ,  G06F11/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/04 ,  G11C29/42 ,  G11C29/44 ,  H01L21/822 ,  H01L27/04 ,  G11C29/00 ,  G06F11/00 ,  G11B20/20

CPC分类号： G06F11/1068 ,  G11C29/42 ,  G11C29/44

摘要： A method of marking an initial defective block in a semiconductor memory device having a memory area thereof divided into a plurality of blocks and provided with an ECC function includes the steps of detecting an initial defective block; and writing an ECC code causing an ECC error in a predetermined area of the initial defective block.

摘要翻译： 一种在半导体存储器件中标记初始缺陷块的方法，该半导体存储器件具有划分成多个块并具有ECC功能的存储区，包括检测初始缺陷块的步骤; 以及在初始缺陷块的预定区域中写入导致ECC错误的ECC码。

公开(公告)号：US06697287B2

公开(公告)日：2004-02-24

申请号：US10259525

申请日：2002-09-30

申请人： Hideyuki Furukawa

发明人： Hideyuki Furukawa

IPC分类号： G11C700

CPC分类号： G06F13/1673 ,  G06F13/1694 ,  G11C16/06

摘要： A data buffer of a memory controller receives first program data, whose size is smaller than that of a page buffer, from a system, and holds the received data. A data adding circuit of the memory controller adds mask data to the first program data, to generate second program data whose size is equal to that of the page buffer. Since the mask data are not programmed to memory cells, only the first program data, which are supplied from the system, are programmed to pages of a nonvolatile semiconductor memory. Namely, even when the size of the page buffer of the nonvolatile semiconductor memory is large, it is possible to maintain interchangeability with an exiting system only by using the memory controller of the present invention.

摘要翻译： 存储器控制器的数据缓冲器从系统接收尺寸小于页面缓冲器的第一程序数据，并保存接收到的数据。 存储器控制器的数据添加电路将掩模数据添加到第一程序数据，以产生尺寸等于页缓冲器的第二程序数据。 由于掩模数据未被编程到存储器单元，所以仅从系统提供的第一程序数据被编程到非易失性半导体存储器的页面。 也就是说，即使当非易失性半导体存储器的页面缓冲器的大小较大时，也可以通过使用本发明的存储器控​​制器来保持与现有系统的互换性。

公开(公告)号：US07046574B2

公开(公告)日：2006-05-16

申请号：US10207079

申请日：2002-07-30

申请人： Hideyuki Furukawa

发明人： Hideyuki Furukawa

IPC分类号： G11C7/00

CPC分类号： G06F12/0292 ,  G06F3/0601 ,  G06F12/1433 ,  G06F2003/0694 ,  G06F2212/2022

摘要： A memory system having a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for controlling the semiconductor storage device is provided. The control section receives a designating signal for designating one area out of the plural areas of the semiconductor storage device and a relative physical address independent by each area and specifies the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address so that the semiconductor storage device is accessed.

公开(公告)号：US06781913B2

公开(公告)日：2004-08-24

申请号：US10207079

申请日：2002-07-30

申请人： Hideyuki Furukawa

发明人： Hideyuki Furukawa

IPC分类号： G11C700

摘要： A memory system having a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for controlling the semiconductor storage device is provided. The control section receives a designating signal for designating one area out of the plural areas of the semiconductor storage device and a relative physical address independent by each area and specifies the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address so that the semiconductor storage device is accessed.

公开(公告)号：US07233994B1

公开(公告)日：2007-06-19

申请号：US09703802

申请日：2000-11-02

申请人： Naoki Koga ,  Naoya Imahashi ,  Souichi Kawata ,  Mitsuhiro Koba ,  Tomiya Miyazaki ,  Tetsuya Tobeta ,  Hideyuki Furukawa ,  Shoichiro Kikuchi

发明人： Naoki Koga ,  Naoya Imahashi ,  Souichi Kawata ,  Mitsuhiro Koba ,  Tomiya Miyazaki ,  Tetsuya Tobeta ,  Hideyuki Furukawa ,  Shoichiro Kikuchi

IPC分类号： G06F15/16 ,  G06F15/173

CPC分类号： H04L12/2856 ,  H04L12/2898 ,  H04L29/12009 ,  H04L29/12226 ,  H04L29/12367 ,  H04L29/12839 ,  H04L61/2015 ,  H04L61/2514 ,  H04L61/6022

摘要： The present invention relates to a network connection apparatus for connecting a plurality of network terminals to an external network such as the Internet. In accordance with the present invention, there provides an easy-to-use network connection apparatus capable of building up an easy and flexible network system by providing the user with plurality types of interface. Specifically, the network connection apparatus comprises a first interface unit including at least one physical layer for connecting to an external network, a second interface unit including a plurality of physical layers for connecting to an internal network, and a controller for controlling the first interface unit and the second interface unit, wherein the second interface unit is capable of independent operation from the first interface unit, and the controller transmits and receives information between the first interface unit and second interface unit, and between the second interface units.

摘要翻译： 本发明涉及一种用于将多个网络终端连接到诸如因特网的外部网络的网络连接装置。 根据本发明，提供一种易于使用的网络连接装置，其能够通过向用户提供多种类型的接口来建立简单而灵活的网络系统。 具体而言，网络连接装置具有包括至少一个用于连接到外部网络的物理层的第一接口单元，包括用于连接到内部网络的多个物理层的第二接口单元，以及用于控制第一接口单元 和第二接口单元，其中第二接口单元能够从第一接口单元独立操作，并且控制器在第一接口单元和第二接口单元之间以及第二接口单元之间发送和接收信息。