公开(公告)号：US08114726B2

公开(公告)日：2012-02-14

申请号：US12923550

申请日：2010-09-28

申请人： Toshiharu Marui ,  Hideyuki Okita

发明人： Toshiharu Marui ,  Hideyuki Okita

IPC分类号： H01L21/336

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462

摘要： In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.

摘要翻译： 在形成栅极凹部的方法中，在包括外延基板的外延晶片的表面上，具有在深度方向上具有带隙能量变化的半导体层和SiN表面保护层，其具有侧壁形成 开口并涂覆外延基板的表面，照射具有与特定半导体层的带隙能量相当的能量的紫外光，同时使用SiN表面保护层从栅极开口光电化学蚀刻特定半导体层 作为面具。 因此获得了没有等离子体离子诱导的损伤的栅极凹槽。

公开(公告)号：US20080272443A1

公开(公告)日：2008-11-06

申请号：US12149325

申请日：2008-04-30

申请人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

发明人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

IPC分类号： H01L29/78 ,  H01L29/778

CPC分类号： H01L29/402 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/812

摘要： A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies.

摘要翻译： 场效应晶体管包括形成在半导体衬底上的有源层，在有源层上彼此分开形成的源极和漏极，形成在源极和漏极之间的栅极，形成在有源层上的第一层间膜， 第一场板（FP）电极，连接到栅电极并设置在栅极和漏极之间的第一层间膜上，形成在第一层间膜上的第二层间膜和连接到源极的第二FP电极， 在第一FP和漏电极之间的第二层间膜。 提供了在高频下表现出较高增益系数的场效应晶体管。

公开(公告)号：US20080283844A1

公开(公告)日：2008-11-20

申请号：US12149823

申请日：2008-05-08

申请人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

发明人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787

摘要： An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.

摘要翻译： 用于形成栅电极的开口由形成在绝缘膜上的第一光致抗蚀剂图案提供。 通过电感耦合等离子体的反应离子蚀刻通过第一光致抗蚀剂图案作为掩模施加到绝缘膜，从而暴露GaN半导体层的表面，在其上蒸发诸如NiAu的栅极金属，由此通过自对准形成栅极电极 处理。 这防止在半导体层的表面上形成氧化膜。 在形成栅电极之后，形成第二光致抗蚀剂图案，以通过第二光致抗蚀剂图案作为掩模在栅电极和绝缘膜上形成场板。 由此，可以使用与由SiN等制成的绝缘膜具有高粘接性的Ti作为场板金属。

公开(公告)号：US20080210977A1

公开(公告)日：2008-09-04

申请号：US11902307

申请日：2007-09-20

申请人： Hideyuki Okita

发明人： Hideyuki Okita

IPC分类号： H01L29/78 ,  H01L29/737

CPC分类号： H01L29/7787 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/7371 ,  H01L2224/06102 ,  H01L2924/01012 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/00

摘要： A semiconductor device includes a support substrate and a semiconductor layer formed on the underlying substrate. The support substrate has its metal part formed by plating and extending across its entire thickness, whilst it has the other region made of semiconductor part. In particular, the region of the support substrate lying immediately below an active region is the metal part formed by plating. The region of the support substrate lying immediately below the region other than the active region is an inactive region made of semiconductor. The semiconductor device thus suppresses warping of a substrate otherwise caused by stress in the metal part formed by plating, and heat evolved due to the current in operation of the semiconductor device may be dissipated over the shortest path through the metal part having a higher thermal conductivity.

摘要翻译： 半导体器件包括支撑衬底和形成在下面的衬底上的半导体层。 支撑基板的金属部分通过电镀而形成，并且跨越其整个厚度延伸，同时其具有由半导体部件制成的另一区域。 特别地，位于有源区域正下方的支撑基板的区域是通过电镀形成的金属部分。 位于紧邻有源区以外的区域的支撑基板的区域是由半导体构成的无效区域。 因此，半导体器件抑制由电镀形成的金属部件中的应力引起的基板的翘曲，并且由于半导体器件的工作中的电流而放出的热可以通过具有较高导热性的金属部件的最短路径消散 。

公开(公告)号：US07812372B2

公开(公告)日：2010-10-12

申请号：US11902307

申请日：2007-09-20

申请人： Hideyuki Okita

发明人： Hideyuki Okita

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/7371 ,  H01L2224/06102 ,  H01L2924/01012 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/00

摘要： A semiconductor device includes a support substrate and a semiconductor layer formed on the underlying substrate. The support substrate has its metal part formed by plating and extending across its entire thickness, whilst it has the other region made of semiconductor part. In particular, the region of the support substrate lying immediately below an active region is the metal part formed by plating. The region of the support substrate lying immediately below the region other than the active region is an inactive region made of semiconductor. The semiconductor device thus suppresses warping of a substrate otherwise caused by stress in the metal part formed by plating, and heat evolved due to the current in operation of the semiconductor device may be dissipated over the shortest path through the metal part having a higher thermal conductivity.

摘要翻译： 半导体器件包括支撑衬底和形成在下面的衬底上的半导体层。 支撑基板的金属部分通过电镀而形成，并且跨越其整个厚度延伸，同时其具有由半导体部件制成的另一区域。 特别地，位于有源区域正下方的支撑基板的区域是通过电镀形成的金属部分。 位于紧邻有源区以外的区域的支撑基板的区域是由半导体构成的无效区域。 因此，半导体器件抑制由电镀形成的金属部件中的应力引起的基板的翘曲，并且由于半导体器件的工作中的电流而放出的热可以通过具有较高导热性的金属部件的最短路径消散 。

公开(公告)号：US07811872B2

公开(公告)日：2010-10-12

申请号：US12149823

申请日：2008-05-08

申请人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

发明人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

IPC分类号： H01L21/338

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787

摘要： An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.

摘要翻译： 用于形成栅电极的开口由形成在绝缘膜上的第一光致抗蚀剂图案提供。 通过电感耦合等离子体的反应离子蚀刻通过第一光致抗蚀剂图案作为掩模施加到绝缘膜，从而暴露GaN半导体层的表面，在其上蒸发诸如NiAu的栅极金属，由此通过自对准形成栅极电极 处理。 这防止在半导体层的表面上形成氧化膜。 在形成栅电极之后，形成第二光致抗蚀剂图案，以通过第二光致抗蚀剂图案作为掩模在栅电极和绝缘膜上形成场板。 由此，可以使用与由SiN等制成的绝缘膜具有高粘接性的Ti作为场板金属。

公开(公告)号：US20100224911A1

公开(公告)日：2010-09-09

申请号：US12659374

申请日：2010-03-05

申请人： Hideyuki Okita ,  Shinichi Hoshi

发明人： Hideyuki Okita ,  Shinichi Hoshi

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/66462

摘要： There is provided a gallium nitride high electron mobility transistor including: a channel layer that lets a carrier travel at high velocity; a carrier supply layer that generates the carrier; and a cap layer, disposed on the carrier supply layer and functioning to prevent oxidation of the carrier supply layer, to reduce gate leakage current, and to increase voltage withstand to gate voltage, wherein a thickness of the cap layer is set at a minimum as thicker than 11 nm.

摘要翻译： 提供了一种氮化镓高电子迁移率晶体管，包括：使载流子高速行进的沟道层; 产生载体的载体供给层; 以及盖层，其设置在所述载体供给层上并且用于防止载体供给层的氧化，以减小栅极泄漏电流，并且增加对栅极电压的耐受电压，其中所述盖层的厚度设定为最小为 厚于11nm。

公开(公告)号：US20060214187A1

公开(公告)日：2006-09-28

申请号：US11378324

申请日：2006-03-20

申请人： Juro Mita ,  Hideyuki Okita ,  Fumihiko Toda

发明人： Juro Mita ,  Hideyuki Okita ,  Fumihiko Toda

IPC分类号： H01L29/739 ,  H01L21/336

CPC分类号： H01L29/66462 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/7787

摘要： A wafer for semiconductor device fabrication, from which large output power can be obtained by making the off-state breakdown voltage higher than in the prior art. The wafer for semiconductor device fabrication comprises a substrate, GaN electron transit layer formed on the side of the principal surface of the substrate, and AlGaN electron supply layer formed on the electron transit layer. The thickness of the electron transit layer is from 0.2 to 0.9 μm.

摘要翻译： 一种用于半导体器件制造的晶片，通过使截止状态击穿电压高于现有技术，可获得大的输出功率。 用于半导体器件制造的晶片包括形成在衬底的主表面侧的衬底，GaN电子转移层以及形成在电子迁移层上的AlGaN电子供给层。 电子转运层的厚度为0.2〜0.9μm。

公开(公告)号：US20110073912A1

公开(公告)日：2011-03-31

申请号：US12923550

申请日：2010-09-28

申请人： Toshiharu Marui ,  Hideyuki Okita

发明人： Toshiharu Marui ,  Hideyuki Okita

IPC分类号： H01L29/737 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462

摘要： In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.

摘要翻译： 在形成栅极凹部的方法中，在包括外延基板的外延晶片的表面上，具有在深度方向上具有带隙能量变化的半导体层和SiN表面保护层，其具有侧壁形成 开口并涂覆外延基板的表面，照射具有与特定半导体层的带隙能量相当的能量的紫外光，同时使用SiN表面保护层从栅极开口光电化学蚀刻特定半导体层 作为面具。 因此获得了没有等离子体离子诱导的损伤的栅极凹槽。

公开(公告)号：US20090001381A1

公开(公告)日：2009-01-01

申请号：US12153953

申请日：2008-05-28

申请人： Toshiharu Marui ,  Hideyuki Okita ,  Shinichi Hoshi ,  Fumihiko Toda

发明人： Toshiharu Marui ,  Hideyuki Okita ,  Shinichi Hoshi ,  Fumihiko Toda

IPC分类号： H01L29/778

CPC分类号： H01L29/0653 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device includes a substrate, laminated layers provided on the substrate. The laminated layers include an AlGaN barrier layer as an uppermost layer. A gate electrode is provided in a channel region of the laminated layers. A source electrode and a drain electrode are provided so as to face each other via the channel region interposed therebetween. A silicon nitride film is formed to cover an exposed surface of the laminated layers exposed via the gate electrode, the source electrode and the drain electrode. The silicon nitride film has characteristics that an etching rate thereof is in a range from 1 nm per/min to 2 nm/min for an etchant in which hydrofluoric acid having a concentration of 50 weight percent and ammonium fluoride having a concentration of 40 weight percent are mixed at a mixing ratio of 1:9.

摘要翻译： 半导体器件包括衬底，设置在衬底上的层叠层。 层叠层包括作为最上层的AlGaN阻挡层。 栅电极设置在层叠层的沟道区域中。 源电极和漏电极经由插入其间的沟道区域彼此面对地设置。 形成氮化硅膜以覆盖经由栅电极，源电极和漏电极露出的层叠层的暴露表面。 氮化硅膜的特征在于，对于浓度为50重量％的氢氟酸和浓度为40重量％的氟化铵的蚀刻剂，其蚀刻速率在1nm / min〜2nm / min的范围内 以1:9的混合比混合。