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    Method for fabricating AIGaN/GaN-HEMT using selective regrowth
    2.
    发明申请
    Method for fabricating AIGaN/GaN-HEMT using selective regrowth 审中-公开
    使用选择性再生长制造AIGaN / GaN-HEMT的方法

    公开(公告)号：US20080176366A1

    公开(公告)日：2008-07-24

    申请号：US11984015

    申请日：2007-11-13

    申请人： Juro Mita ,  Fumihiko Toda ,  Toshiharu Marui

    发明人： Juro Mita ,  Fumihiko Toda ,  Toshiharu Marui

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462

    摘要： A semiconductor body includes, on a substrate, a stack of buffer layer, UID-GaN layer overlying the buffer layer, and UID-AlGaN layer overlying the UID-GaN layer. On the surface of the UID-AlGaN layer, an insulation film is deposited and patterned. An n+-GaN layer is selectively regrown directly on a region of the surface of the semiconductor body other than the insulation film using the patterned insulation film as a mask without etching the surface of the semiconductor body. A portion of the selectively regrown n+-GaN layer corresponding to a region reserved for an ohmic contact electrode is defined and the ohmic contact electrode is formed on the region. An opening exposing a region reserved for a gate electrode is defined and formed within the insulation SiO2 layer, and a gate electrode is formed in the region. An AlGaN/GaN-HEMT or MIS type of AlGaN/GaN-HEMT has lower contact resistance and uniform device characteristics.

    摘要翻译： 半导体本体在衬底上包括一叠缓冲层，覆盖缓冲层的UID-GaN层和覆盖在UID-GaN层上的UID-AlGaN层。 在UID-AlGaN层的表面上，淀积并图案化绝缘膜。 在不蚀刻半导体本体的表面的情况下，使用图案化的绝缘膜作为掩模，在半导体本体的除了绝缘膜之外的区域的区域上选择性地重新生长n + SUP / GaN。 限定与欧姆接触电极保留的区域对应的部分选择性再生长的n + S + GaN层，并且在该区域上形成欧姆接触电极。 在绝缘SiO 2层内限定并形成露出用于栅电极的区域的开口，并且在该区域中形成栅电极。 AlGaN / GaN-HEMT或MIS型AlGaN / GaN-HEMT具有较低的接触电阻和均匀的器件特性。

    Etching method, method of fabricating metal film structure, and etching structure
    3.
    发明授权
    Etching method, method of fabricating metal film structure, and etching structure 失效
    蚀刻方法，金属膜结构的制造方法和蚀刻结构

    公开(公告)号：US07393791B2

    公开(公告)日：2008-07-01

    申请号：US11512341

    申请日：2006-08-30

    申请人： Katsuaki Kaifu ,  Juro Mita

    发明人： Katsuaki Kaifu ,  Juro Mita

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31116 ,  H01L21/7688 ,  Y10T428/24174

    摘要： There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a substrate, a protective film formed on the substrate, a photoresist layer formed on the protective film, and a hole formed throughout the photoresist layer. The hole comprises an opening formed in the photoresist layer surface and a hollow linked to the opening in the thickness direction of the photoresist layer and reaching the protective film. ICP-RIE is performed under conditions such that (1) ICP power is 20 to 100 W, (2) RIE power is 5 to 50 W, and (3) the pressure in the etching chamber is 1 to 100 mTorr.

    摘要翻译： 提供一种蚀刻方法，其中通过ICP-RIE去除存在于衬底结构的蚀刻目的地区域中的保护膜，以形成衬底的主表面的曝光区域。 衬底结构包括衬底，形成在衬底上的保护膜，形成在保护膜上的光致抗蚀剂层和在整个光致抗蚀剂层上形成的孔。 孔包括形成在光致抗蚀剂层表面中的开口和在光致抗蚀剂层的厚度方向上连接到开口的中空并到达保护膜。 ICP-RIE在（1）ICP功率为20〜100W的条件下进行，（2）RIE功率为5〜50W，（3）蚀刻室内的压力为1〜100mTorr。

    Etching structure
    4.
    发明申请
    Etching structure 审中-公开
    蚀刻结构

    公开(公告)号：US20080241469A1

    公开(公告)日：2008-10-02

    申请号：US12153867

    申请日：2008-05-27

    申请人： Katsuaki Kaifu ,  Juro Mita

    发明人： Katsuaki Kaifu ,  Juro Mita

    IPC分类号： B32B7/00

    CPC分类号： H01L21/31116 ,  H01L21/7688 ,  Y10T428/24174

    摘要： An etching structure includes a substrate, a to be etched filmcovering the principal surface of the substrate, and an exposure region exposing the principal surface of the substrate and obtained by removing a part of the to be etched film. A region of the to be etched film constitutes a peripheral region surrounding the exposure region. Another region of the to be etched film outside the peripheral region constitutes a flat region. The film thickness of the to be etched film increases as the distance from the exposure region increases, such that the inclination of the outline of the cross section of the to be etched film that exists within the peripheral region decreases as the distance from the exposure region increases. The to be etched film has a side wall that extends perpendicularly to the principal surface at a boundary between the peripheral region and the flat region.

    摘要翻译： 蚀刻结构包括：衬底，待蚀刻的膜覆盖衬底的主表面;以及暴露区域，暴露衬底的主表面并通过去除被蚀刻膜的一部分而获得。 被蚀刻膜的区域构成围绕曝光区域的周边区域。 要在周边区域外的被蚀刻膜的另一区域构成平坦区域。 被蚀刻膜的膜厚随着与曝光区域的距离增大而增加，使得存在于周边区域内的被蚀刻膜的截面的轮廓的倾斜度随着与曝光区域的距离而减小 增加 要被蚀刻的膜具有在周边区域和平坦区域之间的边界处垂直于主表面延伸的侧壁。

    Ohmic electrode, method of manufacturing Ohmic electrode, field effect transistor, method of manufacturing field effect transistor, and semiconductor device
    6.
    发明申请
    Ohmic electrode, method of manufacturing Ohmic electrode, field effect transistor, method of manufacturing field effect transistor, and semiconductor device 有权
    欧姆电极，制造欧姆电极，场效应晶体管，制造场效应晶体管的方法和半导体器件

    公开(公告)号：US20070051978A1

    公开(公告)日：2007-03-08

    申请号：US11505301

    申请日：2006-08-17

    申请人： Juro Mita ,  Katsuaki Kaifu

    发明人： Juro Mita ,  Katsuaki Kaifu

    IPC分类号： H01L29/739

    CPC分类号： H01L29/452 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/7783

    摘要： The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.

    摘要翻译： 与将欧姆电极提供到比异质界面更深的情况相比，欧姆电极和电子转移层之间的接触电阻降低。 结果，对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极，包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层，欧姆电极的端部位于电子转移层中，在电子转移层中以 深度等于或大于异质界面。

    Polymer pattern forming method
    8.
    发明授权
    Polymer pattern forming method 失效
    聚合物图案形成方法

    公开(公告)号：US06372411B1

    公开(公告)日：2002-04-16

    申请号：US09261463

    申请日：1999-02-24

    申请人： Takeshi Koyano ,  Yoshinori Maeno ,  Juro Mita ,  Katsuaki Kaifu

    发明人： Takeshi Koyano ,  Yoshinori Maeno ,  Juro Mita ,  Katsuaki Kaifu

    IPC分类号： G03F700

    CPC分类号： G03F7/38 ,  G03F7/027

    摘要： A polymer pattern forming method including the steps of (a) generating radicals in a pattern forming region of a matrix layer which uniformly contains a radical generating agent, thereby forming a patterned latent image due to the radicals in the pattern forming region; and (b) bringing a monomer which polymerizes by radical polymerization into contact with the matrix layer in which the patterned latent image has been or is being formed, to have the radicals which have been or are being generated induce a chain addition polymerization of the monomer so as to form a polymer pattern on the pattern forming region.

    摘要翻译： 一种聚合物图案形成方法，包括以下步骤：（a）在均匀地含有自由基生成剂的基质层的图案形成区域中产生自由基，由此在图案形成区域中由于自由基而形成图案化的潜像; 和（b）使通过自由基聚合聚合的单体与已经或正在形成图案化潜像的基质层接触，使已经或正在生成的基团引起单体的链加成聚合 以在图案形成区域上形成聚合物图案。

    Method of manufacturing field effect transistor having Ohmic electrode in a recess
    10.
    发明授权
    Method of manufacturing field effect transistor having Ohmic electrode in a recess 有权
    在凹槽中制造具有欧姆电极的场效应晶体管的方法

    公开(公告)号：US08202794B2

    公开(公告)日：2012-06-19

    申请号：US13064637

    申请日：2011-04-05

    申请人： Juro Mita ,  Katsuaki Kaifu

    发明人： Juro Mita ,  Katsuaki Kaifu

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L29/06 ,  H01L31/00 ,  H01L29/66

    CPC分类号： H01L29/452 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/7783

    摘要： The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.

    摘要翻译： 与将欧姆电极提供到比异质界面更深的情况相比，欧姆电极和电子转移层之间的接触电阻降低。 结果，对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极，包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层，欧姆电极的端部位于电子转移层中，在电子转移层中以 深度等于或大于异质界面。