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35 条记录 (耗时 0.034 秒)

    Integrating a first contact structure in a gate last process
    4.
    发明授权
    Integrating a first contact structure in a gate last process 有权
    在最后一个进程中集成第一个接触结构

    公开(公告)号：US08035165B2

    公开(公告)日：2011-10-11

    申请号：US12341891

    申请日：2008-12-22

    申请人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

    摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

    摘要翻译： 提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。 所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

    INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS
    7.
    发明申请
    INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS 有权
    在门窗最后一个过程中集成第一个接触结构

    公开(公告)号：US20100052075A1

    公开(公告)日：2010-03-04

    申请号：US12341891

    申请日：2008-12-22

    申请人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L29/78 ,  H01L23/48 ,  H01L21/04

    CPC分类号： H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

    摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

    摘要翻译： 提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。 所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

    Dishing-free gap-filling with multiple CMPs
    9.
    发明申请
    Dishing-free gap-filling with multiple CMPs 有权
    无间隙填充多个CMP

    公开(公告)号：US20090286384A1

    公开(公告)日：2009-11-19

    申请号：US12152380

    申请日：2008-05-14

    申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/306 ,  H01L21/283 ,  H01L21/20 ,  H01L21/461 ,  H01L21/302

    CPC分类号： H01L21/76883 ,  H01L21/76229

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

    摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。 该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

    Dishing-free gap-filling with multiple CMPs
    10.
    发明授权
    Dishing-free gap-filling with multiple CMPs 有权

    公开(公告)号：US08552522B2

    公开(公告)日：2013-10-08

    申请号：US13151666

    申请日：2011-06-02

    申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76883 ,  H01L21/76229

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.