公开(公告)号：US20070211510A1

公开(公告)日：2007-09-13

申请号：US11409628

申请日：2006-04-24

Applicant: Sudhir Madan ,  Sung-Wei Lin ,  John Fong

Inventor： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

IPC: G11C11/22 ,  G11C5/06 ,  G11C11/42

CPC classification number: G11C11/22 ,  H01L27/11502

Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Abstract translation: 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US20050207201A1

公开(公告)日：2005-09-22

申请号：US10805809

申请日：2004-03-22

Applicant: Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

Inventor： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC: G11C11/22 ,  G11C11/24

CPC classification number: G11C11/22

Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Abstract translation: 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US20070038805A1

公开(公告)日：2007-02-15

申请号：US11200390

申请日：2005-08-09

Applicant: Jarrod Eliason ,  Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams

Inventor： Jarrod Eliason ,  Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams

IPC: G06F12/00

CPC classification number: G11C29/848 ,  G11C11/22 ,  G11C29/816

Abstract: A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.

Abstract translation: 公开了处理或处理有缺陷的“晶粒”或非易失性铁电存储器阵列的部分的方案。 在一个示例中，存储器的颗粒小于高和小于行宽的列。 当修复编程组发现部分的地址对应于失败的行地址和故障列地址时，对存储器部分执行替换操作。

公开(公告)号：US20060107095A1

公开(公告)日：2006-05-18

申请号：US11260987

申请日：2005-10-28

Applicant: John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

Inventor： John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

IPC: G06F11/00

CPC classification number: G11C29/50 ,  G11C11/22 ,  G11C2029/5002

Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

Abstract translation: 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

公开(公告)号：US20050105354A1

公开(公告)日：2005-05-19

申请号：US10717146

申请日：2003-11-18

Applicant: Sudhir Madan

Inventor： Sudhir Madan

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A memory circuit and method to improve signal margin is disclosed. The circuit includes a memory array arranged in rows 702, 704, 706 and columns 750, 752 of memory cells. Each row of memory cells is connected to a respective wordline. Each column of memory cells is connected to one of a bitline and a complementary bitline. An active wordline accesses a respective row of memory cells. The memory circuit includes a plurality of precharge circuits 724, 726, 728. Each precharge circuit is connected to a respective column of memory cells and coupled to receive a precharge signal PRE. An active precharge signal renders a respective precharge circuit conductive. A control and decode circuit 700 changes an inactive wordline signal to an active wordline signal while the precharge signal is active.

Abstract translation: 公开了一种改善信号余量的存储电路和方法。 电路包括布置在存储器单元的行702,704,706和列750,752中的存储器阵列。 存储单元的每行连接到相应的字线。 每列存储器单元连接到位线和互补位线之一。 活动字线访问相应行的存储单元。 存储器电路包括多个预充电电路724,726,728。每个预充电电路连接到相应的存储单元列并被耦合以接收预充电信号PRE。 有源预充电信号使相应的预充电电路导通。 当预充电信号有效时，控制和解码电路700将非活动字线信号改变为有效字线信号。

公开(公告)号：US06414359B1

公开(公告)日：2002-07-02

申请号：US08733586

申请日：1996-10-18

Applicant: Sudhir Madan

Inventor： Sudhir Madan

IPC: H01L2711

CPC classification number: H01L27/1104 ,  Y10S257/903

Abstract: A 6T CMOS SRAM cell (100) that increases process margins for a given cell area The cell (100) comprises a pair of cross-coupled inverters (102, 104). Each inverter (102, 104) comprises a p-channel pull-up transistor (106, 108) and a n-channel pull-down transistor (110, 112). The p-channel pull-up transistors (106, 108) are offset in both the vertical and horizonal directions from the n-channel pull-down transistors (110, 112).

Abstract translation: 提供给定单元区域的工艺裕度的6T CMOS SRAM单元（100）。单元（100）包括一对交叉耦合的反相器（102,104）。 每个反相器（102,104）包括p沟道上拉晶体管（106,108）和n沟道下拉晶体管（110,112）。 p沟道上拉晶体管（106,108）在从n沟道下拉晶体管（110,112）的垂直方向和水平方向上偏移。

公开(公告)号：US20070036012A1

公开(公告)日：2007-02-15

申请号：US11191709

申请日：2005-07-28

Applicant: Sudhir Madan ,  Bryan Sheffield

Inventor： Sudhir Madan ,  Bryan Sheffield

IPC: G11C7/00

CPC classification number: G11C7/065 ,  G11C11/22

Abstract: An amplifier circuit and method is disclosed. The amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706,708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726). The control gates of the first and second pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.

Abstract translation: 公开了放大器电路和方法。 放大器电路包括放大器部分（700），均衡部分（770）和激活部分（720）。 放大器部分的P沟道晶体管（702,704）耦合到电源端子（802）。 放大器部分的N沟道晶体管（706,708）分别耦合在P沟道晶体管和第一和第二输入端（760,762）之间。 在激活部分中，第一和第二下拉晶体管（722,724）分别耦合在第一和第二输入端子与第二电源端子（726）之间。 第一和第二下拉晶体管的控制栅极彼此耦合。 在操作中，施加到第一和第二输入端的电压信号被N沟道晶体管放大。 然后施加控制信号以将第一和第二输入端耦合到电源电压。

公开(公告)号：US20050276089A1

公开(公告)日：2005-12-15

申请号：US10866834

申请日：2004-06-14

Applicant: Sudhir Madan ,  John Fong

Inventor： Sudhir Madan ,  John Fong

IPC: G11C11/22 ,  G11C17/00

CPC classification number: G11C11/22

Abstract: Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells (106) during memory access operations to mitigate cell storage node disturbances.

Abstract translation: 提出了方法（50,70）和铁电装置（102），其中脉冲（113）在存储器访问操作期间被选择性地施加到一个或多个未选择的铁电存储器单元（106）的板条（PL），以减轻电池存储 节点干扰。

公开(公告)号：US20080079471A1

公开(公告)日：2008-04-03

申请号：US11937303

申请日：2007-11-08

Applicant: Sung-Wei Lin ,  Sudhir Madan ,  John Fong

Inventor： Sung-Wei Lin ,  Sudhir Madan ,  John Fong

IPC: H03K5/01

CPC classification number: H03K19/00346 ,  H03K19/185

Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850 ) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

Abstract translation: 公开了一种减少字线耦合的存储电路和方法。 电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。 第一导体（710,850）耦合到存储器单元的多个行（702,704和706）。 第一晶体管（810）具有耦合在电压源端子（800）和第一导体（850）之间的电流通路和耦合以接收第一控制信号（PLV）的控制端子。 第二晶体管（820）具有耦合在电压供应端和第一导体之间的电流路径，以及耦合以接收第二控制信号（PLW）的控制端。

公开(公告)号：US20070058413A1

公开(公告)日：2007-03-15

申请号：US11227936

申请日：2005-09-15

Applicant: Sung-Wei Lin ,  Sudhir Madan

Inventor： Sung-Wei Lin ,  Sudhir Madan

IPC: G11C11/22

CPC classification number: G11C11/22 ,  G11C7/12 ,  G11C7/14

Abstract: Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line. The method may further optionally comprise grounding the dummy bit line after pulsing the plate line, and optionally disabling the word line after grounding the dummy bit line to precondition the cell for the next memory operation.

Abstract translation: 描述了用于以避免在存储器阵列的边缘处沿着虚拟位线的存储器单元中的栅极氧化物的过压击穿的方式来操作FeRAM和其它这样的存储器件的方法，所述方法包括在板期间浮置虚拟位线 线脉冲活动。 在本发明的一个实施方式中，该方法被应用于具有板线，伪位线，传输晶体管和铁电存储电容器的FeRAM虚拟单元。 该方法包括首先将虚拟位线接地作为优选的前提条件，然而，如果存储电容器的存储节点以其他方式接地，则该步骤可以被认为是可选步骤。 该方法然后包括浮置虚拟位线，激活与存储器单元相关联的字线，以及脉冲板线。 或者，该方法包括将代替虚拟位线或浮置虚拟位线之前的正电压偏压施加到虚拟位线。 该方法可以进一步可选地包括在脉冲板线之后对虚拟位线进行接地，并且可选地在使虚拟位线接地之后禁用字线，以对单元进行下一个存储器操作的预处理。