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    Ring oscillator
    1.
    发明授权
    Ring oscillator 有权
    环形振荡器

    公开(公告)号：US08754716B2

    公开(公告)日：2014-06-17

    申请号：US13595247

    申请日：2012-08-27

    Applicant: Ying-Chieh Ho ,  Yu-Sheng Yang ,  Chau-Chin Su

    Inventor： Ying-Chieh Ho ,  Yu-Sheng Yang ,  Chau-Chin Su

    IPC: H03K5/15 ,  H03K5/00

    CPC classification number: H03K3/0315

    Abstract: A ring oscillator includes (2N+1) inverting delay circuit cells, and each delay circuit cell has an input port and an output port, where N is an integer larger than zero. Each of these (2N+1) inverting delay circuit cells receives a control voltage, and all of the (2N+1) inverting delay circuit cells are electrically connected with each other in series. Furthermore, the input port of one of the (2N+1) inverting delay circuit cells is electrically connected with the output port of an adjacent delay circuit cell of the (2N+1) inverting delay circuit cells.

    Abstract translation: 环形振荡器包括（2N + 1）个反相延迟电路单元，并且每个延迟电路单元具有输入端口和输出端口，其中N是大于零的整数。 这些（2N + 1）个反相延迟电路单元中的每一个接收控制电压，并且所有（2N + 1）个反相延迟电路单元彼此串联电连接。 此外，（2N + 1）个反相延迟电路单元之一的输入端口与（2N + 1）反相延迟电路单元的相邻延迟电路单元的输出端口电连接。

    SIGNAL DELAY CIRCUIT
    2.
    发明申请
    SIGNAL DELAY CIRCUIT 有权
    信号延迟电路

    公开(公告)号：US20090167399A1

    公开(公告)日：2009-07-02

    申请号：US12123613

    申请日：2008-05-20

    Applicant: Hung-Wen LU ,  Chau-Chin SU

    Inventor： Hung-Wen LU ,  Chau-Chin SU

    IPC: H03H11/26

    CPC classification number: H03H11/26 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00228 ,  H03K2005/00234

    Abstract: A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.

    Abstract translation: 描述包括电容性负载元件的信号延迟电路。 电容性负载元件具有第一输入端，第二输入端和第三输入端。 第一输入端接收第一信号，第二输入端接收到与第一信号反相的第二信号，第三输入端接收控制信号。 容性负载元件的电容随控制信号而变化。

    High-speed serial link clock and data recovery
    3.
    发明申请
    High-speed serial link clock and data recovery 失效
    高速串行链路时钟和数据恢复

    公开(公告)号：US20050207520A1

    公开(公告)日：2005-09-22

    申请号：US10800653

    申请日：2004-03-16

    Applicant: Chau-chin Su ,  Chien-Hsi Lee ,  Hung-Wen Lu ,  Hsueh-Chin Lin ,  Yen-Pin Tseng ,  Chia-Nan Wang ,  Uan-Jiun Liu

    Inventor： Chau-chin Su ,  Chien-Hsi Lee ,  Hung-Wen Lu ,  Hsueh-Chin Lin ,  Yen-Pin Tseng ,  Chia-Nan Wang ,  Uan-Jiun Liu

    IPC: H04L7/00 ,  H04L7/033

    CPC classification number: H04L7/0338 ,  H04L7/005

    Abstract: A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.

    Abstract translation: 时钟和数据恢复系统（“CDR”）包括时钟发生器，用于接收输入数据的半速率相位检测器，编码器，输出恢复时钟的相位选择器，置信计数器和输出恢复数据的多路复用器。 时钟发生器以传输的串行数据的一半速率产生8相时钟信号。 相位检测器以标准采样速率的四倍采样输入数据，采用过采样数据并检测其中的相位变化，即相位超前和滞后。 编码器对相变数据进行编码。 置信计数器接收相变数据，并产生表示相变的累积净效应的信号。 相位选择器从时钟发生器接收置信计数器信号和8相时钟，并确定数据采样的最佳相位。

    Architecture of non-synchronous open loop demodulation circuit in pulse position modulation
    4.
    发明授权
    Architecture of non-synchronous open loop demodulation circuit in pulse position modulation 有权
    脉冲位置调制中非同步开环解调电路的结构

    公开(公告)号：US06292051B1

    公开(公告)日：2001-09-18

    申请号：US09268245

    申请日：1999-03-15

    Applicant: Chau-Chin Su ,  Ming-Hwa Hue ,  Chorng-Kuang Wang

    Inventor： Chau-Chin Su ,  Ming-Hwa Hue ,  Chorng-Kuang Wang

    IPC: H03K904

    CPC classification number: H04L25/4902 ,  H04L2027/0046 ,  H04L2027/0095

    Abstract: A simple demodulation circuit having a reduced hardware cost and an increased using flexibility is provided. Such architecture is used in a pulse position modulation for retrieving a data from a received source signal and includes a transformation circuit operating the source signal to produce a quantized data having a plurality of data slots, a slot address detector electrically connected to the transformation circuit for reaching a peak slot address from addresses of the data slots, and a timing recovery decoder electrically connected to the slot address detector for recovering the data through decoding the peak address.

    Abstract translation: 提供了具有降低的硬件成本和增加的使用灵活性的简单解调电路。 这种架构被用于从接收的源信号中检索数据的脉冲位置调制，并且包括操作源信号以产生具有多个数据时隙的量化数据的变换电路，电连接到变换电路的时隙地址检测器 从数据时隙的地址达到峰值时隙地址，以及电时连接到时隙地址检测器的定时恢复解码器，用于通过解码峰值地址来恢复数据。

    SAMPLE AND HOLD CIRCUIT AND RELATED DATA SIGNAL DETECTING METHOD UTILIZING SAMPLE AND HOLD CIRCUIT
    6.
    发明申请
    SAMPLE AND HOLD CIRCUIT AND RELATED DATA SIGNAL DETECTING METHOD UTILIZING SAMPLE AND HOLD CIRCUIT 有权
    采样和保持电路及相关数据信号检测方法利用样品和保持电路

    公开(公告)号：US20090072869A1

    公开(公告)日：2009-03-19

    申请号：US11854560

    申请日：2007-09-13

    Applicant: Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

    Inventor： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

    IPC: G11C27/02

    CPC classification number: G11C27/024 ,  G11C27/026

    Abstract: Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

    Abstract translation: 公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

    Sample and hold circuit and related data signal detecting method utilizing sample and hold circuit
    7.
    发明授权
    Sample and hold circuit and related data signal detecting method utilizing sample and hold circuit 有权
    采样保持电路及相关数据信号检测方法利用采样保持电路

    公开(公告)号：US07495479B1

    公开(公告)日：2009-02-24

    申请号：US11854560

    申请日：2007-09-13

    Applicant: Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

    Inventor： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

    IPC: H03K17/00

    CPC classification number: G11C27/024 ,  G11C27/026

    Abstract: Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

    Abstract translation: 公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

    Method and system for measuring characteristics of liquid crystal display driver chips
    8.
    发明授权
    Method and system for measuring characteristics of liquid crystal display driver chips 失效
    用于测量液晶显示驱动芯片特性的方法和系统

    公开(公告)号：US06925415B2

    公开(公告)日：2005-08-02

    申请号：US10374441

    申请日：2003-02-25

    Applicant: I-Shih Tseng ,  Chau-Chin Su ,  Wei-Juo Wang

    Inventor： I-Shih Tseng ,  Chau-Chin Su ,  Wei-Juo Wang

    IPC: G09G3/00 ,  G06F17/18 ,  G06F15/00

    CPC classification number: G09G3/006

    Abstract: A measuring method and system for liquid crystal display driver chips applies a new method to measure voltages of driver chips, and utilizes probability and statistics for analysis and determination so as to yield a rather accurate effect even under noisy environments. Accordingly, analog-to-digital converters can be replaced for faster sampling. The measuring method and system can be implemented using comparator circuits or pin electronics cards so that the measuring procedure for driver chips is simplified. Measured results are analyzed and verified by application of probability and statistics. As such, testing of liquid crystal display driver chips is more accurate, testing time is reduced, and accuracy level is promoted.

    Abstract translation: 液晶显示驱动芯片的测量方法和系统应用了一种测量驱动芯片电压的新方法，并利用概率统计学进行分析和确定，即使在嘈杂的环境下也能产生相当准确的效果。 因此，可以替换模数转换器以进行更快的采样。 测量方法和系统可以使用比较器电路或引脚电子卡来实现，从而简化驱动器芯片的测量程序。 通过应用概率和统计量对测量结果进行分析和验证。 因此，液晶显示驱动器芯片的测试更准确，测试时间缩短，提高了精度水平。

    Method and circuit for sampling timing recovery
    9.
    发明授权
    Method and circuit for sampling timing recovery 有权
    采样定时恢复的方法和电路

    公开(公告)号：US06366628B1

    公开(公告)日：2002-04-02

    申请号：US09177223

    申请日：1998-10-22

    Applicant: Chau-Chin Su ,  Lee-Yuang Huang ,  Jin-Jyh Lee ,  Chorng-Kuang Wang

    Inventor： Chau-Chin Su ,  Lee-Yuang Huang ,  Jin-Jyh Lee ,  Chorng-Kuang Wang

    IPC: H04L700

    CPC classification number: H04L7/041 ,  H03L7/091 ,  H03L7/10 ,  H04L7/033

    Abstract: A sampling timing recovering circuit free from being troubled by a frequency error is provided. Such recovering circuit includes a phase locking circuit having a local frequency for processing an incoming signal having a phase, a specific parameter and an input symbol rate and for locking the phase of the incoming signal, and a frequency locking circuit electrically connected to the phase locking circuit for locking the input symbol rate of the incoming signal to enable the phase locking circuit to desiredly process the incoming signal. A method to this effect is also provided and includes the steps of a) processing an incoming signal having a phase, a specific parameter and an input symbol rate to have the phase lockable, b) locking the phase of the incoming signal, and c) locking the input symbol rate of the incoming signal to enable the incoming signal to be predeterminedly processed.

    Abstract translation: 提供了不受频率误差扰动的采样定时恢复电路。 这种恢复电路包括具有用于处理具有相位，特定参数和输入符号率并用于锁定输入信号的相位的输入信号的本地频率的锁相电路，以及电连接到相位锁定的频率锁定电路 用于锁定输入信号的输入符号速率的电路，以使相位锁定电路能够期望地处理输入信号。 还提供了一种这样的方法，包括以下步骤：a）处理具有相位，特定参数和输入符号速率的输入信号以具有相位锁定，b）锁定输入信号的相位，以及c） 锁定输入信号的输入符号速率以使输入信号能够被预先处理。

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