公开(公告)号：US20120025861A1

公开(公告)日：2012-02-02

申请号：US13196380

申请日：2011-08-02

申请人： Hwan Wook PARK ,  Woo Seop KIM ,  Sung Bum CHO

发明人： Hwan Wook PARK ,  Woo Seop KIM ,  Sung Bum CHO

IPC分类号： G01R31/00

CPC分类号： G01R1/045 ,  G01R1/0466

摘要： A test device is provided. The test device includes a first via which transmits a supply voltage, a second via which transmits a ground voltage, a test board including a plurality of test signal vias for transmitting a plurality of test signals, a capacitor disposed on an upper part of the test board and connected between the first via and the second via, and a test socket which electrically connects a device under test (DUT) with the test board. The test socket includes a first region including a flat lower surface bordering the test board, a second region including an uneven lower surface, a plurality of first contactors which are disposed in the first region and which are connected to the plurality of vias, and two second contactors which are disposed in the second region and which are connected to two terminals of the capacitor.

摘要翻译： 提供测试设备。 测试装置包括发送电源电压的第一通孔，发送接地电压的第二通孔，包括用于发送多个测试信号的多个测试信号通孔的测试板，设置在测试的上部的电容器 并连接在第一通孔和第二通孔之间，以及将被测器件（DUT）与测试板电连接的测试插座。 测试插座包括：第一区域，包括与测试板邻接的平坦的下表面，包括不平坦的下表面的第二区域;多个第一接触器，其布置在第一区域中并连接到多个通孔;以及两个 第二接触器，其布置在第二区域中并且连接到电容器的两个端子。

公开(公告)号：US20100315887A1

公开(公告)日：2010-12-16

申请号：US12773177

申请日：2010-05-04

申请人： Hwan-wook Park

发明人： Hwan-wook Park

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/1201 ,  G11C29/48

摘要： A semiconductor memory device includes a plurality of chips, a data path that is physically shared by the plurality of chips, a data input/output pad, and a data output driver. The data output driver is configured to receive merged data that includes data merged from a set of chip data read from the plurality of chips, compare the merged data to first reference data in a test mode, compare the merged data to second reference data in a test mode, and based on the comparisons, apply an output voltage at a data input/output pad.

摘要翻译： 半导体存储器件包括多个芯片，由多个芯片物理共享的数据路径，数据输入/输出焊盘和数据输出驱动器。 数据输出驱动器被配置为接收包括从从多个芯片读取的一组芯片数据合并的数据的合并数据，将合并的数据与测试模式中的第一参考数据进行比较，将合并的数据与第一参考数据进行比较 测试模式，并且基于比较，在数据输入/输出焊盘处施加输出电压。

公开(公告)号：US07681097B2

公开(公告)日：2010-03-16

申请号：US11778161

申请日：2007-07-16

申请人： Hwan-wook Park

发明人： Hwan-wook Park

IPC分类号： G01R31/28 ,  G11C19/00

CPC分类号： G06F11/2733 ,  G01R31/31703 ,  G01R31/31724

摘要： A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the DUT, compressing the serial data bits by m bits (m≧4) in response to a second clock signal to generate a signature signal, and outputting the signature signal to the tester. The tester compares a computed signature signal to a 1-bit signature signal to determine whether the DUT is operating poorly or not.

摘要翻译： 提供了采用压缩数据的测试控制器的测试系统，数据压缩电路和测试方法。 所述测试系统包括测试器，被测器件（DUT）以及接收来自所述DUT的第一时钟信号和串行数据位的测试控制器，响应于所述测试器的串行数据位按m位（m≥4） 第二时钟信号以产生签名信号，并将签名信号输出到测试者。 测试仪将计算出的签名信号与1位签名信号进行比较，以确定DUT是否运行不良。

公开(公告)号：US08325539B2

公开(公告)日：2012-12-04

申请号：US12773177

申请日：2010-05-04

申请人： Hwan-wook Park

发明人： Hwan-wook Park

IPC分类号： G11C7/06

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/1201 ,  G11C29/48

摘要： A semiconductor memory device includes a plurality of chips, a data path that is physically shared by the plurality of chips, a data input/output pad, and a data output driver. The data output driver is configured to receive merged data that includes data merged from a set of chip data read from the plurality of chips, compare the merged data to first reference data in a test mode, compare the merged data to second reference data in a test mode, and based on the comparisons, apply an output voltage at a data input/output pad.

摘要翻译： 半导体存储器件包括多个芯片，由多个芯片物理共享的数据路径，数据输入/输出焊盘和数据输出驱动器。 数据输出驱动器被配置为接收包括从从多个芯片读取的一组芯片数据合并的数据的合并数据，将合并的数据与测试模式中的第一参考数据进行比较，将合并的数据与第一参考数据进行比较 测试模式，并且基于比较，在数据输入/输出焊盘处施加输出电压。

公开(公告)号：US07802154B2

公开(公告)日：2010-09-21

申请号：US11928019

申请日：2007-10-30

申请人： Hwan-wook Park

发明人： Hwan-wook Park

IPC分类号： G11C29/00

CPC分类号： G11C29/40 ,  G11C29/14 ,  G11C2029/3602

摘要： A method and system for testing a semiconductor memory device using low-speed test equipment. The method includes providing a high-frequency test pattern by grouping a command signal and an address signal into command signal groups and address signal groups each corresponding to L cycles of a clock signal output from automatic test equipment (ATE) where L is a natural number. A valid command signal and a valid address signal, which are not in an idle state, are extracted from each of a plurality of command signal groups and each of a plurality of address signal groups. The valid command signal and the valid address signal are compressed into signals having a length corresponding to 1/M (M is a natural number larger than 1) of the cycle of the clock signal where M is a natural number larger than 1. A position designating signal indicating the positions of the valid command signal and the valid address signal in each command signal group and each address signal group is generated. A high-frequency command signal and a high-frequency address signal from the compressed valid command signal and the compressed valid address signal using the position designating signal are generated.

摘要翻译： 一种使用低速测试设备测试半导体存储器件的方法和系统。 该方法包括通过将命令信号和地址信号分组成命令信号组和地址信号组来提供高频测试模式，每个地址信号组各自对应于从自动测试设备（ATE）输出的时钟信号的L个周期，其中L是自然数 。 多个命令信号组和多个地址信号组中的每一个都提取不处于空闲状态的有效命令信号和有效地址信号。 有效命令信号和有效地址信号被压缩为长度对应于M是大于1的自然数的时钟信号周期的1 / M（M是大于1的自然数）的信号。位置 指示每个指令信号组和每个地址信号组中的有效指令信号和有效地址信号的位置的指示信号。 产生来自压缩的有效命令信号的高频命令信号和高频地址信号以及使用位置指示信号的压缩有效地址信号。

公开(公告)号：US07673209B2

公开(公告)日：2010-03-02

申请号：US11832093

申请日：2007-08-01

申请人： Hwan-wook Park ,  Young-uk Chang

发明人： Hwan-wook Park ,  Young-uk Chang

IPC分类号： G06F11/00

CPC分类号： G11C29/14 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/56004 ,  G11C2029/3602

摘要： Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a plurality of register blocks which receive test signals input from an external tester through an input/output pad and load the test signals into the resister blocks in synchronization with a low-frequency clock signal; a register block control unit which controls the activation of the register blocks; and an output unit which is connected to the register blocks and outputs the signals loaded into the register blocks as test patterns in synchronization with a high-frequency clock signal.

摘要翻译： 提供一种产生具有各种类型和长度的测试图案的测试图形生成电路和使用该测试图形生成电路进行测试操作的半导体存储器件。 测试图形生成电路包括多个寄存器块，其通过输入/输出焊盘接收从外部测试器输入的测试信号，并将测试信号与低频时钟信号同步地加载到寄存器块中; 寄存器块控制单元，其控制寄存器块的激活; 以及输出单元，其连接到寄存器块，并且与高频时钟信号同步地将加载到寄存器块中的信号作为测试图案输出。

公开(公告)号：US20080106966A1

公开(公告)日：2008-05-08

申请号：US11979424

申请日：2007-11-02

申请人： Hwan-Wook Park ,  Woo-Seop Kim

发明人： Hwan-Wook Park ,  Woo-Seop Kim

IPC分类号： G11C11/00 ,  G05F1/10

CPC分类号： G11C5/143

摘要： A power-up/power-down detecting circuit may include a power detecting circuit, a selecting circuit, and a determining circuit. The power detecting circuit may generate a plurality of detection signals based on a plurality of sensing signals corresponding to currents flowing through a plurality of function blocks. The selecting circuit may generate a plurality of selection signals. The determining circuit may generate a power-up completion signal and a power-down completion signal. A semiconductor device having the power-up/power-down detecting circuit may determine in real time the power-up time and the power-down time.

摘要翻译： 上电/断电检测电路可以包括功率检测电路，选择电路和确定电路。 功率检测电路可以基于与流过多个功能块的电流相对应的多个感测信号来生成多个检测信号。 选择电路可以产生多个选择信号。 确定电路可以产生上电完成信号和掉电完成信号。 具有上电/断电检测电路的半导体器件可以实时地确定上电时间和断电时间。

公开(公告)号：US20090207895A1

公开(公告)日：2009-08-20

申请号：US12379080

申请日：2009-02-12

申请人： Hwan-Wook Park ,  Young-Chan Jang

发明人： Hwan-Wook Park ,  Young-Chan Jang

IPC分类号： H04B1/38

CPC分类号： G11C8/18 ,  G11C7/1003 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C2207/2254 ,  H04L1/004

摘要： A data transceiver system may include an error corrector. The error corrector may include a plurality of delay units, each delay unit being configured to delay a corresponding data signal among a plurality of data signals by a time in response to a corresponding delay code among a plurality of delay codes and outputting the delayed data signal, an error detector configured to receive the plurality of delay codes, determine whether an error has occurred, and output an error signal according to the determination in a data frame lock operation, and a delay controller configured to set initial values of the plurality of delay codes to a predetermined value, vary and output each of the plurality of delay codes in response to a lock signal, and reset initial values the plurality of delay codes in response to the error signal in the data frame lock operation.

摘要翻译： 数据收发器系统可以包括错误校正器。 错误校正器可以包括多个延迟单元，每个延迟单元被配置为响应于多个延迟代码之间的对应的延迟代码延迟多个数据信号之间的相应数据信号，并输出延迟的数据信号 ，配置为接收所述多个延迟码的错误检测器，确定是否发生错误，并且根据数据帧锁定操作中的确定输出错误信号;以及延迟控制器，被配置为设置所述多个延迟的初始值 编码到预定值，响应于锁定信号改变并输出多个延迟码中的每一个，并且响应于数据帧锁定操作中的错误信号来复位初始值多个延迟码。

公开(公告)号：US07498847B2

公开(公告)日：2009-03-03

申请号：US11654813

申请日：2007-01-18

申请人： Hwan-Wook Park

发明人： Hwan-Wook Park

IPC分类号： H03K19/086 ,  H03F1/14

CPC分类号： H03K19/018585 ,  G11C7/1051 ,  G11C7/1069 ,  G11C29/1201 ,  G11C29/48

摘要： An output driver of a semiconductor memory device that operates in a differential mode and in a single mode is disclosed. The output driver includes a current supplying circuit that operates as a resistor in a single mode and as a current source in a differential mode. Accordingly, the semiconductor memory device including the output driver can have high test efficiency, since the number of test pins utilized during a test operation can be selectively reduced for low frequency tests.

摘要翻译： 公开了以差分模式和单模操作的半导体存储器件的输出驱动器。 输出驱动器包括在单模中作为电阻器工作的电流供给电路和作为差分模式的电流源。 因此，包括输出驱动器的半导体存储器件可以具有高的测试效率，因为在低频测试期间可以选择性地降低在测试操作期间使用的测试引脚的数量。

公开(公告)号：US20080086663A1

公开(公告)日：2008-04-10

申请号：US11832093

申请日：2007-08-01

申请人： Hwan-wook PARK ,  Young-uk CHANG

发明人： Hwan-wook PARK ,  Young-uk CHANG

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/56004 ,  G11C2029/3602

摘要： Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a plurality of register blocks which receive test signals input from an external tester through an input/output pad and load the test signals into the resister blocks in synchronization with a low-frequency clock signal; a register block control unit which controls the activation of the register blocks; and an output unit which is connected to the register blocks and outputs the signals loaded into the register blocks as test patterns in synchronization with a high-frequency clock signal.

摘要翻译： 提供一种产生具有各种类型和长度的测试图案的测试图形生成电路和使用该测试图形生成电路进行测试操作的半导体存储器件。 测试图形生成电路包括多个寄存器块，其通过输入/输出焊盘接收从外部测试器输入的测试信号，并将测试信号与低频时钟信号同步地加载到寄存器块中; 寄存器块控制单元，其控制寄存器块的激活; 以及输出单元，其连接到寄存器块，并且与高频时钟信号同步地将加载到寄存器块中的信号作为测试图案输出。