公开(公告)号：US07334169B2

公开(公告)日：2008-02-19

申请号：US11151053

申请日：2005-06-13

申请人： Young-Uk Chang ,  Gil-Shin Moon ,  Dong-Ho Hyun

发明人： Young-Uk Chang ,  Gil-Shin Moon ,  Dong-Ho Hyun

IPC分类号： G01R31/28

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： A memory device includes a plurality of test mode signal generating units and a plurality of test circuits. Each test mode signal generating unit generates a respective test mode signal for a respective test circuit. The test mode signal generating units generate the test mode signals in series for the test circuits. Each test mode signal generating unit may be disposed within a respective test circuit such that wiring is not necessary from the source of the test mode signals to the test circuits.

摘要翻译： 存储器件包括多个测试模式信号发生单元和多个测试电路。 每个测试模式信号产生单元为相应的测试电路产生相应的测试模式信号。 测试模式信号发生单元为测试电路产生串联的测试模式信号。 每个测试模式信号产生单元可以设置在相应的测试电路内，使得不需要从测试模式信号的源到测试电路的布线。

公开(公告)号：US07130232B2

公开(公告)日：2006-10-31

申请号：US10744179

申请日：2003-12-23

申请人： Joung-Yeal Kim ,  Young-Uk Chang ,  Kyoung-Ho Kim

发明人： Joung-Yeal Kim ,  Young-Uk Chang ,  Kyoung-Ho Kim

IPC分类号： G11C7/12

CPC分类号： G11C7/1048 ,  G11C11/4096

摘要： Integrated circuit devices are provided including a pair of differential I/O lines and a driver circuit. The driver circuit is configured to drive the pair of differential I/O lines responsive to a write command signal. First and second precharge circuits are also provided. The first precharge circuit is configured to precharge the pair of differential I/O lines to a first voltage during a first mode of operation responsive to an active command signal. The second precharge circuit is configured to precharge the pair of differential I/O lines to a second voltage, lower than the first voltage, during a second mode of operation responsive to the active command signal. Related methods of operating integrated circuit devices are also provided.

摘要翻译： 集成电路器件包括一对差分I / O线和驱动电路。 驱动器电路被配置为响应于写入命令信号驱动该对差分I / O线。 还提供了第一和第二预充电电路。 第一预充电电路被配置为响应于有效命令信号在第一操作模式期间将一对差分I / O线预充电到第一电压。 第二预充电电路被配置为响应于激活的命令信号在第二操作模式期间将该对差分I / O线预充电到低于第一电压的第二电压。 还提供了操作集成电路器件的相关方法。

公开(公告)号：US06822914B2

公开(公告)日：2004-11-23

申请号：US10459741

申请日：2003-06-12

申请人： Chang-sik Kim ,  Dong-ryul Ryu ,  Hyun-Dong Kim ,  Young-uk Chang ,  Seok-won Hwang

发明人： Chang-sik Kim ,  Dong-ryul Ryu ,  Hyun-Dong Kim ,  Young-uk Chang ,  Seok-won Hwang

IPC分类号： G11C700

CPC分类号： G11C29/12015 ,  G11C29/12 ,  G11C2029/3602

摘要： An integrated circuit memory device includes a test pattern data generator circuit that is configured to generate an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and is configured to provide the extended test pattern data and the test pattern data during a test mode of the memory device. Related methods are also disclosed.

公开(公告)号：US07587645B2

公开(公告)日：2009-09-08

申请号：US11690092

申请日：2007-03-22

申请人： Young-Uk Chang ,  Sang-Woong Shin

发明人： Young-Uk Chang ,  Sang-Woong Shin

IPC分类号： G01R31/28

CPC分类号： G01R31/31917 ,  G01R31/31919 ,  G11C7/1078 ,  G11C29/1201 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/3602

摘要： An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.

摘要翻译： 半导体存储器件的输入电路包括数据输入电路和数据图形设定电路。 数据输入电路接收第一数据，并通过缓冲第一数据产生第二数据，响应于写入数据选通（WDQS）信号采样缓冲的第一数据，并且并行采样数据。 数据模式设置电路响应于测试模式信号和数据模式选择信号设置第二数据的模式以产生第三数据。 因此，包括输入电路的半导体存储器件可以在测试模式下生成各种图案的数据，并且可以使用低速测试器进行高速测试。

公开(公告)号：US08730751B2

公开(公告)日：2014-05-20

申请号：US13467188

申请日：2012-05-09

申请人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

发明人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

摘要翻译： 提供一种用于控制延迟锁定环（DLL）电路的操作的半导体存储器件。 半导体存储器件包括DLL电路，其接收外部时钟信号，并且对外部时钟信号和内部时钟信号执行锁定操作，由此获得锁定状态。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。

公开(公告)号：US20120218848A1

公开(公告)日：2012-08-30

申请号：US13467188

申请日：2012-05-09

申请人： JUN-BAE KIM ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

发明人： JUN-BAE KIM ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

摘要翻译： 提供一种用于控制延迟锁定环（DLL）电路的操作的半导体存储器件。 半导体存储器件包括DLL电路，其接收外部时钟信号，并且对外部时钟信号和内部时钟信号执行锁定操作，由此获得锁定状态。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。

公开(公告)号：US07612578B2

公开(公告)日：2009-11-03

申请号：US11585615

申请日：2006-10-24

申请人： Young-Uk Chang ,  Dong-Ho Hyun ,  Seok-Won Hwang

发明人： Young-Uk Chang ,  Dong-Ho Hyun ,  Seok-Won Hwang

IPC分类号： H03K17/16 ,  H03K19/003 ,  G06F13/00

CPC分类号： G01R31/318572 ,  G01R31/3172 ,  H04L25/0298

摘要： A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.

摘要翻译： 公开了半导体器件，测试系统和测试芯片端接（ODT）电路的方法。 半导体器件包括ODT电路，终端阻抗控制电路和边界扫描电路。 终端阻抗控制电路响应于测试模式命令产生终止阻抗控制信号。 ODT电路耦合到多个输入/输出焊盘，并且响应于阻抗控制信号产生多个终端阻抗。 边界扫描电路存储终端阻抗以输出存储的终端阻抗。 因此，半导体器件可以通过使用较少数量的引脚来精确地测试ODT电路，并且可以减少测试半导体器件所需的时间。

公开(公告)号：US20080086663A1

公开(公告)日：2008-04-10

申请号：US11832093

申请日：2007-08-01

申请人： Hwan-wook PARK ,  Young-uk CHANG

发明人： Hwan-wook PARK ,  Young-uk CHANG

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/56004 ,  G11C2029/3602

摘要： Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a plurality of register blocks which receive test signals input from an external tester through an input/output pad and load the test signals into the resister blocks in synchronization with a low-frequency clock signal; a register block control unit which controls the activation of the register blocks; and an output unit which is connected to the register blocks and outputs the signals loaded into the register blocks as test patterns in synchronization with a high-frequency clock signal.

摘要翻译： 提供一种产生具有各种类型和长度的测试图案的测试图形生成电路和使用该测试图形生成电路进行测试操作的半导体存储器件。 测试图形生成电路包括多个寄存器块，其通过输入/输出焊盘接收从外部测试器输入的测试信号，并将测试信号与低频时钟信号同步地加载到寄存器块中; 寄存器块控制单元，其控制寄存器块的激活; 以及输出单元，其连接到寄存器块，并且与高频时钟信号同步地将加载到寄存器块中的信号作为测试图案输出。

公开(公告)号：US20060059398A1

公开(公告)日：2006-03-16

申请号：US11151053

申请日：2005-06-13

申请人： Young-Uk Chang ,  Gil-Shin Moon ,  Dong-Ho Hyun

发明人： Young-Uk Chang ,  Gil-Shin Moon ,  Dong-Ho Hyun

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： A memory device includes a plurality of test mode signal generating units and a plurality of test circuits. Each test mode signal generating unit generates a respective test mode signal for a respective test circuit. The test mode signal generating units generate the test mode signals in series for the test circuits. Each test mode signal generating unit may be disposed within a respective test circuit such that wiring is not necessary from the source of the test mode signals to the test circuits.

摘要翻译： 存储器件包括多个测试模式信号发生单元和多个测试电路。 每个测试模式信号产生单元为相应的测试电路产生相应的测试模式信号。 测试模式信号发生单元为测试电路产生串联的测试模式信号。 每个测试模式信号产生单元可以设置在相应的测试电路内，使得不需要从测试模式信号的源到测试电路的布线。

公开(公告)号：US08184495B2

公开(公告)日：2012-05-22

申请号：US12580585

申请日：2009-10-16

申请人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

发明人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

摘要翻译： 用于控制延迟锁定环（DLL）电路的操作的半导体存储器件包括接收外部时钟信号并对外部时钟信号和内部时钟信号执行锁定操作的DLL电路，从而获得锁定状态 。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。