公开(公告)号：US20080018377A1

公开(公告)日：2008-01-24

申请号：US11621251

申请日：2007-01-09

Applicant: Hwi-Taek Chung

Inventor： Hwi-Taek Chung

IPC: G11C5/14 ,  G11C7/04

CPC classification number: G11C7/04 ,  G11C5/143

Abstract: A semiconductor memory device controlling an output voltage level of a high voltage generator according to a variation of temperature has a high voltage generator that provides a high voltage higher than a power source voltage through an output terminal, generates a temperature detection signal obtained by sensing a variation of a diode current according to a temperature variation, and adjusts a voltage level of the output terminal in response to the temperature detection signal. The device is able to automatically control an output voltage or current of the high voltage generator. Accordingly, it is possible to control fluctuation of output voltage level or current level due to a voltage variation, thereby lessening degradation of program or erasure characteristics of memory cells that is caused from the fluctuation of the output voltage or current.

Abstract translation: 根据温度变化控制高电压发生器的输出电压电平的半导体存储器件具有通过输出端提供高于电源电压的高电压的高电压发生器，产生通过感测 根据温度变化的二极管电流的变化，并响应于温度检测信号调整输出端子的电压电平。 该装置能够自动控制高压发生器的输出电压或电流。 因此，可以通过电压变化来控制输出电压电平或电流电平的波动，从而降低由输出电压或电流的波动引起的存储单元的程序劣化或擦除特性。

公开(公告)号：US07298190B2

公开(公告)日：2007-11-20

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US06940758B2

公开(公告)日：2005-09-06

申请号：US10421160

申请日：2003-04-23

Applicant: Hwi-Taek Chung

Inventor： Hwi-Taek Chung

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/08 ,  G11C16/0425

Abstract: A flash memory device provides for a stable source line regardless of bit line coupling during a read operation and regardless of loading effect during a manufacturing process. The flash memory device includes: a plurality of flash memory cells arranged in rows and columns, each of the flash memory cells having a control gate, a source and a drain; a plurality of first, odd-numbered word lines each of which is connected with corresponding control gate of a first set of the flash memory cells; a plurality of second, even-numbered word lines each of which is connected with corresponding control gate of a second set of the flash memory cells; a plurality of bit lines each of which is connected with corresponding a drain of the flash memory cells; and a plurality of selection transistors connected between a source line and a discharge line, the source line being connected to sources of the first and second sets of flash memory cells, the selection transistors comprising the same structure as the first and second sets of the flash memory cells.

Abstract translation: 闪存器件在读取操作期间提供稳定的源极线，而不管位线耦合，而不管制造过程中的负载效应如何。 闪速存储器件包括：以行和列排列的多个闪存单元，每个闪存单元具有控制栅极，源极和漏极; 多个第一奇数字线，其每一个与闪存单元的第一组的相应控制栅极连接; 多个第二偶数字线，每个字线与第二组闪存单元的相应控制栅极连接; 多个位线与闪存单元的漏极相对应连接; 以及连接在源极线和放电线之间的多个选择晶体管，所述源极线连接到所述第一和第二组闪存单元的源极，所述选择晶体管包括与所述第一和第二组闪存相同的结构 记忆细胞

公开(公告)号：US6128231A

公开(公告)日：2000-10-03

申请号：US448077

申请日：1999-11-23

Applicant: Hwi-Taek Chung

Inventor： Hwi-Taek Chung

IPC: G11C16/02 ,  G11C16/00 ,  G11C16/06 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/12

Abstract: Disclosed herein is a nonvolatile semiconductor memory device which comprises a voltage level sensing circuit for detecting whether a word line voltage and a bit line voltage are boosted up to their target levels for a program operation. When the voltages are boosted up to the target levels, the voltage level sensing circuit generates a pulse signal for indicating that the word line and bit line voltages are sufficiently boosted up to the target levels. The nonvolatile semiconductor memory device realized according to this scheme can reduce a program time when it is implemented using the higher power supply voltage. Therefore, optimized program time of the memory device according to the present invention is secured.

Abstract translation: 这里公开了一种非易失性半导体存储器件，其包括电压电平检测电路，用于检测字线电压和位线电压是否升高到用于编程操作的目标电平。 当电压升高到目标电平时，电压电平检测电路产生用于指示字线和位线电压被充分提升到目标电平的脉冲信号。 根据该方案实现的非易失性半导体存储器件可以在使用更高的电源电压实现时减少编程时间。 因此，确保了根据本发明的存储器件的优化的程序时间。

公开(公告)号：US6101126A

公开(公告)日：2000-08-08

申请号：US167534

申请日：1998-10-07

Applicant: Hwi-Taek Chung ,  Jong-Min Park

Inventor： Hwi-Taek Chung ,  Jong-Min Park

IPC: G11C16/06 ,  G11C5/14 ,  G11C16/08 ,  G11C16/12 ,  G11C13/00

CPC classification number: G11C16/12 ,  G11C16/08

Abstract: A nonvolatile semiconductor device which includes a word line, a bit line, and a memory cell connected to the word line and the bit line, also has a word line driving circuit for driving the word line with a word line voltage supplied in response to a shut off signal in accordance with each mode of operation, and a circuit for generating the shut off signal during each mode of operation. The circuit generates the shut off signal which has a power supply voltage when the word line voltage is higher than the power supply voltage, and has the word line voltage when the word line voltage is less than the power supply voltage.

Abstract translation: 包括字线，位线和连接到字线和位线的存储单元的非易失性半导体器件还具有字线驱动电路，用于驱动字线，该字线响应于供给的字线电压 根据每个操作模式切断信号，以及用于在每个操作模式期间产生关断信号的电路。 当字线电压高于电源电压时，该电路产生具有电源电压的截止信号，并且当字线电压小于电源电压时具有字线电压。

公开(公告)号：US07606099B2

公开(公告)日：2009-10-20

申请号：US11621251

申请日：2007-01-09

Applicant: Hwi-Taek Chung

Inventor： Hwi-Taek Chung

IPC: G11C7/00

CPC classification number: G11C7/04 ,  G11C5/143

Abstract: A semiconductor memory device controlling an output voltage level of a high voltage generator in response to a variation of temperature has a high voltage generator that provides a high voltage higher than a power source voltage through an output terminal, generates a temperature detection signal obtained by sensing a variation of a diode current based on a temperature variation, and adjusts a voltage level of the output terminal in response to the temperature detection signal. The device is able to automatically control an output voltage or current of the high voltage generator.

Abstract translation: 响应于温度变化控制高电压发生器的输出电压电平的半导体存储器件具有通过输出端子提供高于电源电压的高电压的高电压发生器，产生通过感测获得的温度检测信号 基于温度变化的二极管电流的变化，并且响应于温度检测信号来调节输出端子的电压电平。 该装置能够自动控制高压发生器的输出电压或电流。

公开(公告)号：US20060139073A1

公开(公告)日：2006-06-29

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US06580644B1

公开(公告)日：2003-06-17

申请号：US10091048

申请日：2002-03-04

Applicant: Hwi-Taek Chung

Inventor： Hwi-Taek Chung

IPC: G11C1606

CPC classification number: G11C29/50004 ,  G11C16/04 ,  G11C16/30 ,  G11C16/344 ,  G11C16/349 ,  G11C29/50

Abstract: A nonvolatile semiconductor memory device is provided, which supports an erase verify operation mode to determine whether an erased memory cell is lower than a maximal threshold voltage (e.g., 3V), and a test verify operation mode to determine whether the erased memory cell has a progressive fail characteristic. Once the memory device enters the test verify operation mode, a wordline voltage to be applied to a memory cell and a reference wordline voltage to be applied to a reference cell are generated. The wordline and reference wordline voltages generated in the test verify operation mode are set to be higher than those generated in the erase verify operation mode. This makes it possible to compare current flowing through the memory cell and reference cell at more than one level and to check a memory cell for a progressive (or potential) failing characteristic.

Abstract translation: 提供了一种非易失性半导体存储器件，其支持擦除验证操作模式以确定擦除的存储器单元是否低于最大阈值电压（例如3V），以及测试验证操作模式以确定擦除的存储器单元是否具有 渐进失败特征。 一旦存储器件进入测试验证操作模式，就产生要施加到存储单元的字线电压和要施加到参考单元的参考字线电压。 在测试验证操作模式中产生的字线和参考字线电压被设置为高于在擦除验证操作模式中产生的字线和参考字线电压。 这使得可以比较流过多于一个电平的存储单元和参考单元的电流，并检查存储单元是否存在渐进（或潜在的）故障特性。

公开(公告)号：US06301177B1

公开(公告)日：2001-10-09

申请号：US09457576

申请日：1999-12-09

Applicant: Hwi-Taek Chung

Inventor： Hwi-Taek Chung

IPC: G11C700

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C5/147

Abstract: A memory device includes first, second, and third discharging units, which are connected to a negative voltage node, for discharging the negative voltage to a ground voltage through three steps which are sequentially conductive. The first discharging unit discharges the negative voltage in response to a first signal and a second signal. It does so when the negative voltage is a first voltage level. The second discharging unit discharges the negative voltage in response to the second signal and a third signal. It does so when the negative voltage is a second voltage level. The third discharging unit discharges the negative voltage in response to a fourth signal and a fifth signal. It does so when the negative voltage is a third voltage level.

Abstract translation: 存储装置包括连接到负电压节点的第一，第二和第三放电单元，用于通过依次导通的三个步骤将负电压排出到接地电压。 第一放电单元响应于第一信号和第二信号而放电负电压。 当负电压是第一电压电平时，这样做。 第二放电单元响应于第二信号和第三信号而放电负电压。 当负电压是第二电压电平时，这样做。 第三放电单元响应于第四信号和第五信号而放电负电压。 当负电压是第三电压电平时，这样做。

公开(公告)号：US6122194A

公开(公告)日：2000-09-19

申请号：US491846

申请日：2000-01-26

Applicant: Hwi-Taek Chung ,  Jong-Min Park

Inventor： Hwi-Taek Chung ,  Jong-Min Park

IPC: G11C29/04 ,  G11C7/00 ,  G11C8/00 ,  G11C16/06 ,  G11C29/00

CPC classification number: G11C29/785

Abstract: A semiconductor memory device is provided which comprises a mat having a plurality of sectors for storing information of data; and a redundancy circuit for generating a plurality of redundancy selection signals to be applied in common to the sectors when the enable fuse element is open-circuited. Each of the sectors comprises a main memory cell array and the redundancy memory cell array divided into two redundant bit segments, each of which has two redundant columns of redundant memory cells. Each sector further comprises a first column selector for selecting one of the main columns of each bit segment in response to first column address signals; a second column selector for selecting one of the two redundant columns of each redundant bit segment in response to one of the first column address signals; and a third column selector for selecting one of the two bit segments in each input/output block and one of the two redundant bit segments in response to second column address signals. Furthermore, each sector has a plurality of sense amplifiers for sensing and amplifying stored data in corresponding main column and; redundant column thus selected; and a plurality of multiplexers each for receiving outputs from a first corresponding sense amplifier and from the second sense amplifier and selecting one of the outputs thus received in response to a corresponding redundancy selection signal.

Abstract translation: 提供了一种半导体存储器件，其包括具有用于存储数据信息的多个扇区的垫; 以及冗余电路，用于在所述使能熔丝元件断开时产生要被共同施加到所述扇区的多个冗余选择信号。 每个扇区包括主存储单元阵列，并且冗余存储单元阵列被划分为两个冗余位段，每个冗余位段具有冗余存储单元的两个冗余列。 每个扇区还包括第一列选择器，用于响应于第一列地址信号选择每个位段的主列之一; 第二列选择器，用于响应于所述第一列地址信号之一来选择每个冗余位段的两个冗余列之一; 以及第三列选择器，用于响应于第二列地址信号，选择每个输入/输出块中的两个位段之一和两个冗余位段中的一个。 此外，每个扇区具有多个读出放大器，用于感测和放大相应主列中存储的数据; 选择冗余列; 以及多个多路复用器，每个用于接收来自第一对应读出放大器和第二读出放大器的输出，并且响应于相应的冗余选择信号选择如此接收的输出之一。