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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140073099A1

    公开(公告)日：2014-03-13

    申请号：US13967492

    申请日：2013-08-15

    申请人： KWANGMIN PARK ,  BYONGJU KIM ,  JUMI YUN ,  JAEYOUNG AHN

    发明人： KWANGMIN PARK ,  BYONGJU KIM ,  JUMI YUN ,  JAEYOUNG AHN

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/42332 ,  H01L29/7889 ,  H01L29/7926

    摘要： A semiconductor device has a vertical channel and includes a first tunnel insulating layer adjacent to a blocking insulating layer, a third tunnel insulating layer adjacent to a channel pillar, and a second tunnel insulating layer between the first and third tunnel insulating layers. The energy band gap of the third tunnel insulating layer is smaller than that of the first tunnel insulating layer and is larger than that of the second tunnel insulating layer.

    摘要翻译： 半导体器件具有垂直沟道，并且包括与隔离绝缘层相邻的第一隧道绝缘层，与沟道柱相邻的第三隧道绝缘层和在第一和第三隧道绝缘层之间的第二隧道绝缘层。 第三隧道绝缘层的能带隙小于第一隧道绝缘层的能带隙，并且大于第二隧道绝缘层的能带隙。

    METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    4.
    发明申请
    METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权
    制造三维半导体存储器件的方法

    公开(公告)号：US20120295409A1

    公开(公告)日：2012-11-22

    申请号：US13475023

    申请日：2012-05-18

    申请人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

    发明人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

    IPC分类号： H01L21/336 ,  H01L21/31 ,  H01L21/28 ,  H01L21/302

    CPC分类号： H01L27/11582 ,  H01L21/31 ,  H01L29/7926

    摘要： Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

    摘要翻译： 制造三维半导体存储器件的方法包括：将具有绝缘层和牺牲层的叠层结构形成在衬底上的层叠层，形成将板堆结构分成多个模具结构的第一和第二沟槽，第一沟槽位于 第二沟槽，在第一和第二沟槽中形成第一垂直绝缘隔板，形成穿透模具结构并与第一和第二沟槽隔开的半导体图案，从第二沟槽移除第一垂直绝缘隔板以暴露牺牲层，去除 所述牺牲层由所述第二沟槽暴露以形成部分地暴露所述半导体图案和所述第一垂直绝缘隔板的凹部区域，以及在所述凹部区域中形成导电图案。

    Nonvolatile memory devices and methods of fabricating the same
    5.
    发明授权
    Nonvolatile memory devices and methods of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US09490371B2

    公开(公告)日：2016-11-08

    申请号：US14539043

    申请日：2014-11-12

    申请人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    发明人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/115

    CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

    摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

    摘要翻译： 非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储 垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。 电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。 第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

    Methods of fabricating three-dimensional semiconductor memory devices
    6.
    发明授权
    Methods of fabricating three-dimensional semiconductor memory devices 有权
    制造三维半导体存储器件的方法

    公开(公告)号：US09397114B2

    公开(公告)日：2016-07-19

    申请号：US13475023

    申请日：2012-05-18

    申请人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

    发明人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

    IPC分类号： H01L27/00 ,  H01L21/00 ,  H01L27/115 ,  H01L21/31 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L21/31 ,  H01L29/7926

    摘要： Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

    摘要翻译： 制造三维半导体存储器件的方法包括：将具有绝缘层和牺牲层的叠层结构形成在衬底上的层叠层，形成将板堆结构分成多个模具结构的第一和第二沟槽，第一沟槽位于 第二沟槽，在第一和第二沟槽中形成第一垂直绝缘隔板，形成穿透模具结构并与第一和第二沟槽隔开的半导体图案，从第二沟槽移除第一垂直绝缘隔板以暴露牺牲层，去除 所述牺牲层由所述第二沟槽暴露以形成部分地暴露所述半导体图案和所述第一垂直绝缘隔板的凹部区域，以及在所述凹部区域中形成导电图案。

    Nonvolatile Memory Devices And Methods Of Fabricating The Same
    7.
    发明申请
    Nonvolatile Memory Devices And Methods Of Fabricating The Same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20150194440A1

    公开(公告)日：2015-07-09

    申请号：US14539043

    申请日：2014-11-12

    申请人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    发明人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

    IPC分类号： H01L27/115 ,  H01L29/792

    CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

    摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

    摘要翻译： 非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储 垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。 电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。 第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。