利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

48 条记录 (耗时 0.026 秒)

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150340376A1

    公开(公告)日：2015-11-26

    申请号：US14620770

    申请日：2015-02-12

    申请人： Jintaek PARK ,  Sunghoi HUR ,  Jang-Hyun YOU

    发明人： Jintaek PARK ,  Sunghoi HUR ,  Jang-Hyun YOU

    IPC分类号： H01L27/115 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.

    摘要翻译： 根据示例性实施例，包括具有单元和连接区域的衬底，堆叠在单元区域上的栅电极，垂直沟道结构，焊盘，虚拟柱以及第一和第二半导体图案的三维半导体器件。 垂直沟道结构穿透最下面的栅电极上的栅极，并且包括第一栅极电介质图案。 焊盘从栅电极延伸并且堆叠在连接区域上。 虚拟柱穿透最低垫上的一些焊盘并且包括第二栅极电介质图案。 第一半导体图案在垂直沟道结构和衬底之间。 第二半导体图案位于虚拟柱和衬底之间。 第一和第二栅极电介质图案可以分别在第一和第二半导体图案上。 第二栅极电介质图案可以覆盖第二半导体图案的整个顶表面。

    Nonvolatile memory including memory cell array having three-dimensional structure
    4.
    发明授权
    Nonvolatile memory including memory cell array having three-dimensional structure 有权
    包括具有三维结构的存储单元阵列的非易失性存储器

    公开(公告)号：US08987832B2

    公开(公告)日：2015-03-24

    申请号：US14080823

    申请日：2013-11-15

    申请人： Jintaek Park ,  Youngwoo Park

    发明人： Jintaek Park ,  Youngwoo Park

    IPC分类号： H01L27/088 ,  H01L27/115 ,  H01L27/24 ,  H01L29/423 ,  H01L29/792

    CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/792

    摘要： A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other.

    摘要翻译： 提供了一种非易失性存储器，其包括多个通道层和多个绝缘层，所述多个绝缘层沿垂直于所述衬底的方向交替堆叠在衬底上，所述多个沟道层中的每一个包括沿着第一方向延伸的多个沟道膜 与基板平行的平面; 多个导电材料，其从沟道层的顶部和绝缘层延伸到与基板垂直的方向上的与衬底相邻的部分，通过每个沟道层的沟道膜之间的区域; 设置在沟道层的沟道膜和导电材料之间的多个信息存储膜; 以及分别连接到沟道层的多个位线，其中沟道层的导电材料，信息存储膜和沟道膜形成三维存储单元阵列，其中导电材料形成多个组 并且其中所述组之间的距离长于彼此之间的导电材料之间的距离。

    Semiconductor Devices and Methods of Fabricating the Same
    5.
    发明申请
    Semiconductor Devices and Methods of Fabricating the Same 有权
    半导体器件及其制造方法

    公开(公告)号：US20150061155A1

    公开(公告)日：2015-03-05

    申请号：US14469611

    申请日：2014-08-27

    申请人： YuJeong Seo ,  JinTaek PARK ,  Youngwoo PARK

    发明人： YuJeong Seo ,  JinTaek PARK ,  Youngwoo PARK

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.

    摘要翻译： 本发明构思提供半导体器件及其制造方法。 根据该方法，重复堆叠具有预定高度和活动孔的子堆叠结构。 因此，可以改善电池分散，并且可以防止在蚀刻工艺中引起的各种误差，例如不开放的误差。 作为通道使用的活性柱的粒径可以使用金属诱导横向结晶法增加或最大化，从而可提高电池电流。 可以控制包括结晶诱导金属的金属硅化物层的形成位置，使得可以根据活性柱中的位置来控制结晶诱导金属的浓度等级。

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20140085961A1

    公开(公告)日：2014-03-27

    申请号：US14037547

    申请日：2013-09-26

    申请人： Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

    发明人： Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

    IPC分类号： G11C5/06 ,  G11C13/00

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

    摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

    SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED RESISTIVE MEMORY CELLS
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED RESISTIVE MEMORY CELLS 有权
    具有三维电阻记忆细胞的半导体存储器件

    公开(公告)号：US20130134377A1

    公开(公告)日：2013-05-30

    申请号：US13606789

    申请日：2012-09-07

    申请人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

    发明人： Jintaek PARK ,  Youngwoo PARK ,  Jungdal CHOI

    IPC分类号： H01L27/26 ,  H01L27/22

    CPC分类号： H01L27/249 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

    摘要： Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

    摘要翻译： 提供半导体存储器件。 该装置可以包括彼此连接以构成选择线组的第一和第二选择线，顺序地堆叠在第一和第二选择线中的每一个上的多个字线，在第一和第二选择线之间排列成一行的垂直电极 选择线，在选择线组的两侧中的每一侧排列成行的多个位线插头以及与字线交叉并将位线插头彼此连接的位线。

    Semiconductor memory device and method of fabricating the same
    10.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09530789B2

    公开(公告)日：2016-12-27

    申请号：US14701985

    申请日：2015-05-01

    申请人： Joonhee Lee ,  Jintaek Park

    发明人： Joonhee Lee ,  Jintaek Park

    IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

    摘要： Semiconductor memory devices and methods of fabricating the same are provided. A semiconductor memory device includes stack gate structures that are spaced apart from each other in a first direction horizontal to a substrate. Each of the stack gate structures includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. Vertical channel structures penetrate the stack gate structures. A source plug line is provided between the stack gate structures. The source plug line is in contact with the substrate and extends in a second direction intersecting the first direction. The substrate being in contact with the source plug line includes a plurality of protruding regions formed along the second direction. Each of the protruding regions has a first width, and the protruding regions are spaced apart from each other by a first distance greater than the first width.

    摘要翻译： 提供半导体存储器件及其制造方法。 一种半导体存储器件包括在与衬底水平的第一方向上彼此间隔开的堆叠栅极结构。 堆叠栅极结构中的每一个包括绝缘层和栅极电极交替地且重复堆叠在基板上。 垂直通道结构穿透堆叠门结构。 在堆叠门结构之间提供源插头线。 源插头线与衬底接触并沿与第一方向相交的第二方向延伸。 与源插头线接触的衬底包括沿着第二方向形成的多个突起区域。 每个突出区域具有第一宽度，并且突出区域彼此间隔开大于第一宽度的第一距离。