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    PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME
    1.
    发明申请
    PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME 有权
    具有改进的字线电阻的相变存储器件及其制造方法

    公开(公告)号：US20120329222A1

    公开(公告)日：2012-12-27

    申请号：US13605167

    申请日：2012-09-06

    Applicant: Mi Ra CHOI ,  Jang Uk LEE

    Inventor： Mi Ra CHOI ,  Jang Uk LEE

    IPC: H01L21/8239

    CPC classification number: H01L27/0207 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/7833 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.

    Abstract translation: 提出了具有改进的字线电阻的相变存储器件及其制造方法。 相变存储器件包括半导体衬底，字线，层间绝缘膜，捆扎线，多个电流路径，开关元件和相变可变电阻器。 字线形成在半导体衬底的单元区域中。 形成在字线上的层间绝缘膜。 捆扎线形成在层间绝缘膜上，使得捆扎线与字线的顶部重叠。 电流路径将字线与捆扎线电连接在一起。 开关元件电连接到捆扎线。 相变可变电阻器电连接到开关元件。

    METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE
    2.
    发明申请
    METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE 有权
    使用交叉图形技术制造相位变化记忆装置的方法

    公开(公告)号：US20110143477A1

    公开(公告)日：2011-06-16

    申请号：US12834141

    申请日：2010-07-12

    Applicant: Jang Uk LEE ,  Kang Sik CHOI ,  Hae Chan PARK ,  Jin Hyock KIM ,  Ja Chun KU

    Inventor： Jang Uk LEE ,  Kang Sik CHOI ,  Hae Chan PARK ,  Jin Hyock KIM ,  Ja Chun KU

    IPC: H01L21/28

    CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

    Abstract: A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.

    Abstract translation: 提供一种制造相变存储器件的方法。 在半导体衬底上形成具有以恒定距离隔开的多个金属字线的第一绝缘层。 形成具有阻挡金属层，多晶硅层和硬掩模层的多个线结构以覆盖在多个金属字线上。 在线路结构之间形成第二绝缘层。 通过使用与金属字线交叉的掩模图案蚀刻线结构的硬掩模层和多晶硅层来形成交叉图案。 第三绝缘层埋在交叉图案之间的空间内。 形成自对准的相变接触孔，同时，通过选择性地去除构成交叉图案的硬掩模层，形成由剩余多晶硅层形成的二极管图案。

    SEMICONDUCTOR MEMORY DEVICE HAVING CELL PATTERNS ON INTERCONNECTION AND FABRICATION METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING CELL PATTERNS ON INTERCONNECTION AND FABRICATION METHOD THEREOF 有权
    具有互连的细胞图案的半导体存储器件及其制造方法

    公开(公告)号：US20130099386A1

    公开(公告)日：2013-04-25

    申请号：US13598303

    申请日：2012-08-29

    Applicant: Jang Uk LEE

    Inventor： Jang Uk LEE

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

    Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

    Abstract translation: 提供一种具有形成在互连上并能够降低互连电阻的单元图形的半导体存储器件及其制造方法。 半导体器件包括其中限定了单元区域，核心区域和外围区域并形成底部结构的半导体基板，形成在半导体基板的整个结构上的导电线，形成在该半导体基板上的存储单元图案 电池区域中的导线，以及形成在芯区域和外围区域中的导电线中的任一个上的虚设导电图案。

    PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME
    4.
    发明申请
    PHASE CHANGE MEMORY DEVICE HAVING AN IMPROVED WORD LINE RESISTANCE, AND METHODS OF MAKING SAME 有权
    具有改进的字线电阻的相变存储器件及其制造方法

    公开(公告)号：US20100327249A1

    公开(公告)日：2010-12-30

    申请号：US12635950

    申请日：2009-12-11

    Applicant: Mi Ra CHOI ,  Jang Uk LEE

    Inventor： Mi Ra CHOI ,  Jang Uk LEE

    IPC: H01L45/00 ,  H01L29/18 ,  H01L21/06

    CPC classification number: H01L27/0207 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/7833 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.

    Abstract translation: 提出了具有改进的字线电阻的相变存储器件及其制造方法。 相变存储器件包括半导体衬底，字线，层间绝缘膜，捆扎线，多个电流路径，开关元件和相变可变电阻器。 字线形成在半导体衬底的单元区域中。 形成在字线上的层间绝缘膜。 捆扎线形成在层间绝缘膜上，使得捆扎线与字线的顶部重叠。 电流路径将字线与捆扎线电连接在一起。 开关元件电连接到捆扎线。 相变可变电阻器电连接到开关元件。

    METHOD AND APPARATUS FOR IMPROVING BROADCASTING RECEPTION PERFORMANCE OF PORTABLE TERMINAL
    5.
    发明申请
    METHOD AND APPARATUS FOR IMPROVING BROADCASTING RECEPTION PERFORMANCE OF PORTABLE TERMINAL 有权
    改善便携式终端广播接收性能的方法和装置

    公开(公告)号：US20100035540A1

    公开(公告)日：2010-02-11

    申请号：US12509805

    申请日：2009-07-27

    Applicant: Sung Won KIM ,  Jae Min Seo ,  Jung Su Lee ,  Jae Kwang Lee ,  Jang Uk Lee

    Inventor： Sung Won KIM ,  Jae Min Seo ,  Jung Su Lee ,  Jae Kwang Lee ,  Jang Uk Lee

    IPC: H04H60/09

    CPC classification number: H04B1/525 ,  H04B1/1036

    Abstract: The present invention relates to a portable terminal, and to a method and apparatus for improving broadcasting reception performance of the portable terminal by filtering a transmission frequency of a radio frequency unit introduced to a broadcasting reception path without experiencing broadcast signal loss. The filtering can be achieved using a filter that includes a variable capacitor in the broadcasting reception path. Accordingly, the transmission frequency of the radio frequency unit may be filtered without a broadcast signal loss. A capacitance of the variable capacitor may be controlled according to the broadcast channel.

    Abstract translation: 便携式终端技术领域本发明涉及便携式终端，以及通过对引入到广播接收路径的射频单元的发送频率进行滤波而不经历广播信号丢失来提高便携式终端的广播接收性能的方法和装置。 可以使用在广播接收路径中包括可变电容器的滤波器来实现滤波。 因此，无线广播信号丢失可以对射频单元的发送频率进行滤波。 可以根据广播信道来控制可变电容器的电容。

    Semiconductor memory device having dummy conductive patterns on interconnection
    6.
    发明授权
    Semiconductor memory device having dummy conductive patterns on interconnection 有权
    在互连上具有虚设导电图案的半导体存储器件

    公开(公告)号：US08759979B2

    公开(公告)日：2014-06-24

    申请号：US13598303

    申请日：2012-08-29

    Applicant: Jang Uk Lee

    Inventor： Jang Uk Lee

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

    Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

    Abstract translation: 提供一种具有形成在互连上并能够降低互连电阻的单元图形的半导体存储器件及其制造方法。 半导体器件包括其中限定了单元区域，核心区域和外围区域并形成底部结构的半导体基板，形成在半导体基板的整个结构上的导电线，形成在该半导体基板上的存储单元图案 电池区域中的导线，以及形成在芯区域和外围区域中的导电线中的任一个上的虚设导电图案。

    PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    相变随机访问存储器件及其制造方法

    公开(公告)号：US20120326112A1

    公开(公告)日：2012-12-27

    申请号：US13331448

    申请日：2011-12-20

    Applicant: Jang Uk LEE

    Inventor： Jang Uk LEE

    IPC: H01L47/00 ,  H01L21/02

    CPC classification number: H01L45/1233 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144

    Abstract: A phase-change random access memory (PCRAM) device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, a junction word line formed on the semiconductor substrate, an epitaxial word line formed on the junction word line, and a switching device formed on the epitaxial word line.

    Abstract translation: 提供了相变随机存取存储器（PCRAM）装置及其制造方法。 PCRAM装置包括半导体衬底，形成在半导体衬底上的结字线，形成在结字线上的外延字线以及形成在外延字线上的开关器件。

    PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND FABRICATION METHOD THEREOF
    10.
    发明申请
    PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND FABRICATION METHOD THEREOF 有权
    具有减少干扰的相变存储器件及其制造方法

    公开(公告)号：US20110147689A1

    公开(公告)日：2011-06-23

    申请号：US12782839

    申请日：2010-05-19

    Applicant: Jang Uk LEE

    Inventor： Jang Uk LEE

    IPC: H01L45/00 ,  H01L21/06

    CPC classification number: H01L28/20 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A phase change memory device capable of reducing disturbances between adjacent PRAM memory cells and a fabrication method are presented. The phase change memory device includes word lines, heating electrodes, an interlayer insulating layer, and a phase change lines. The word lines are formed on a semiconductor substrate and extend in parallel with a constant space. The heating electrodes are electrically connected to the plurality of word lines. The interlayer insulating layer insulates the heating electrodes. The phase change lines extend in a direction orthogonal to the word line and are electrically connected to the heating electrodes. Curves are formed on a surface of the interlayer insulating layer between the word lines such that the effective length of the phase change layer between adjacent heating electrodes is larger than the physical distance between the adjacent heating electrodes.

    Abstract translation: 提出了能够减少相邻PRAM存储单元之间的干扰的相变存储器件和制造方法。 相变存储器件包括字线，加热电极，层间绝缘层和相变线。 字线形成在半导体衬底上并且以恒定的空间平行延伸。 加热电极与多条字线电连接。 层间绝缘层绝热加热电极。 相变线在与字线正交的方向上延伸并且电连接到加热电极。 在字线之间的层间绝缘层的表面上形成曲线，使得相邻加热电极之间的相变层的有效长度大于相邻加热电极之间的物理距离。

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