公开(公告)号：US07084074B1

公开(公告)日：2006-08-01

申请号：US09575349

申请日：2000-05-19

申请人： Michael J. D'Elia ,  Barry Sheffield ,  Raymond Branstetter ,  Jayendra D. Bhakta

发明人： Michael J. D'Elia ,  Barry Sheffield ,  Raymond Branstetter ,  Jayendra D. Bhakta

IPC分类号： H01L21/31

CPC分类号： C23C16/45578 ,  C23C16/4583

摘要： Chemical vapor deposition (CVD) is enhanced by compensating for a depleted gas concentration zone in a CVD reactor. According to an example embodiment of the present invention, a chemical-vapor deposition (CVD) gas injector is adapted to supply gas to a CVD chamber in a manner that enhances the properties of deposited films. The injector has a gas inlet coupled to a gas source and supplies gas from the source to the CVD system via at least one gas outlet. The injector is adapted to deliver gas in a manner that sufficiently maintains uniform supply of the gas in a zone of the CVD system that would exhibit a depleted gas supply absent the injector. The uniform gas supply improves the CVD process in various manners, including making possible the deposition of films having uniform properties, such as reflectivity, extinction coefficient, thickness and refractive index.

摘要翻译： 通过补偿CVD反应器中的贫化气体浓度区域来增强化学气相沉积（CVD）。 根据本发明的示例性实施例，化学气相沉积（CVD）气体注入器适于以提高沉积膜性质的方式向CVD室供应气体。 喷射器具有连接到气体源的气体入口，并且经由至少一个气体出口将气体从源提供给CVD系统。 喷射器适于以如下方式输送气体：在CVD系统的区域中充分保持气体均匀供应的方式，其将在没有喷射器的情况下显示耗尽气体供应。 均匀的气体供给以各种方式改善CVD工艺，包括使得具有均匀性质的膜的沉积，例如反射率，消光系数，厚度和折射率。

公开(公告)号：US06303507B1

公开(公告)日：2001-10-16

申请号：US09487180

申请日：2000-01-19

申请人： Weizhong Wang ,  Jayendra D. Bhakta

发明人： Weizhong Wang ,  Jayendra D. Bhakta

IPC分类号： H01L21302

CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  B24B49/16

摘要： To attenuate a CMP polishing rate differential which tends to occur over the surface of a semiconductor substrate surface which has had one or more layers formed thereon, surface characteristics of the upper surface which are representative of the thickness, for example, of a layer which is being removed either in part or in its entirety, are monitored and surface profile information is developed using a suitable algorithm and used to control the timing with which force is applied by one or more of a plurality of actuators disposed on the other side of the wafer, in a manner wherein areas which have undergone more removal than others, are forced into contact with the polishing pad with a force which is reduced as compared that which is applied to localized high areas wherein a lesser amount of the layer has been removed.

摘要翻译： 为了衰减倾向于在其上形成有一层或多层的半导体衬底表面的表面上发生的CMP抛光速率差异，表示厚度的上表面的表面特性例如为 被部分地或全部地被去除，并且使用合适的算法来开发表面轮廓信息，并且用于控制由设置在晶片的另一侧上的多个致动器中的一个或多个致动器施加力的定时 以与其它方式相比经历更多去除的区域被强制与抛光垫接触的力相比，其被施加到其中较少量的层被去除的局部高区域的力减小。

公开(公告)号：US06645868B1

公开(公告)日：2003-11-11

申请号：US09861990

申请日：2001-05-17

申请人： Carl P. Babcock ,  Jayendra D. Bhakta

发明人： Carl P. Babcock ,  Jayendra D. Bhakta

IPC分类号： H01L21762

CPC分类号： H01L21/76232 ,  Y10S438/95 ,  Y10S438/952

摘要： Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

摘要翻译： 通过最初形成一层高吸收富硅氮化物以在半导体衬底和光致抗蚀剂之间用作硬掩模，来提供晶体管和半导体衬底上的其它器件之间的浅沟槽隔离。 富含氮化物的高吸收层的消光系数（k）> 0.5。 当反射光穿过富含硅的氮化物层时，基本上量的光被吸收在其中，从而阻止这种反射光在光刻期间不利于光刻胶的图案化。 在光致抗蚀剂图案化之后，通过根据形成在光致抗蚀剂上的图案通过富硅氮化物进行蚀刻，在半导体衬底中形成隔离沟槽。

公开(公告)号：US06337264B2

公开(公告)日：2002-01-08

申请号：US09365411

申请日：1999-08-02

申请人： Jayendra D. Bhakta

发明人： Jayendra D. Bhakta

IPC分类号： H01L213205

CPC分类号： H01L21/32139 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/4925 ,  Y10S438/947 ,  Y10S438/952

摘要： Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer of silicon oxime on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon oxime layer in the same tool.

摘要翻译： 通过在图案化之前在多晶硅层上沉积硅肟的抗反射层，形成多晶硅栅极，具有更高的精度和一致性。 实施例还包括在同一工具中沉积多晶硅层和硅肟层。

公开(公告)号：US06605517B1

公开(公告)日：2003-08-12

申请号：US10150282

申请日：2002-05-15

申请人： Jayendra D. Bhakta ,  Krishnashree Achuthan ,  Angela Hui

发明人： Jayendra D. Bhakta ,  Krishnashree Achuthan ,  Angela Hui

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/31053

摘要： A method for reducing nitride residue from a silicon wafer during semiconductor fabrication. The wafer includes a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches. The method includes providing an optimized oxide deposition process in which a temperature gradient of a CVD chamber is improved by performing the following steps. First, at least one silicon wafer is placed into the chamber on a quartz boat having an increased slot size, preferably at least 6 mm. Second, the quartz boat is centered in approximately a center of the chamber so that the wafer is located in a center section of the chamber to avoid the temperature gradient at the ends of the chamber, such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer. The method further includes performing an optimized polishing process on the oxide wherein the oxide is polished down to approximately a level of the nitride, but where more of the oxide is removed from the edge area of the wafer than in the center area. Thereafter, the nitride is stripped from the wafer, wherein substantially all of the nitride is removed from the wafer, thereby minimizing nitride residue.

摘要翻译： 一种用于在半导体制造期间从硅晶片减少氮化物残余物的方法。 晶片包括限定有源区域和隔离区域的氮化物掩模，其中隔离区域由沟槽形成。 该方法包括提供优化的氧化物沉积工艺，其中通过执行以下步骤来改善CVD室的温度梯度。 首先，将至少一个硅晶片放置在具有增加的槽尺寸，优选至少6mm的石英舟皿的室中。 第二，石英舟在大致中心的腔室中心，使得晶片位于腔室的中心部分，以避免腔室端部的温度梯度，使得当氧化物气体注入到晶片上时， 在晶片上形成厚度基本均匀的氧化物层。 该方法还包括对氧化物进行优化的抛光工艺，其中将氧化物抛光至氮化物的大致一定程度，但是从晶片的边缘区域除去氧化物中的比在中心区域更多的氧化物。 此后，从晶片剥离氮化物，其中基本上所有的氮化物从晶片中去除，从而使氮化物残留最小化。

公开(公告)号：US06500774B1

公开(公告)日：2002-12-31

申请号：US09608003

申请日：2000-06-30

申请人： Jayendra D. Bhakta

发明人： Jayendra D. Bhakta

IPC分类号： H01L2131

CPC分类号： H01L21/0276 ,  C23C16/345 ,  H01L21/3185

摘要： Embodiments of the invention comprise a new device and technique to realize an improved throughput of a BARC layer furnace deposition device. This improvement is achieved by providing for a higher flow rate of NH3 during the BARC deposition process. Also, this improvement may be achieved by reducing the temperature gradient of the BARC layer furnace deposition device to approximately 715-750° C. For example, approximately a 1-10% blend of NH3 in at least one of Argon, Nitrogen, and Helium is utilized. By diluting the NH3, a higher flow rate may be utilized in the furnace deposition device, thus allowing for an increased load uniformity of the BARC layer thickness, refractive index, extinction coefficient, and reflectivity characteristics. Also, the NH3 depletion is reduced and preferably eliminated due to the higher flow rate of the diluted NH3. Further, this diluted NH3 allows for a reduced DCS requirement, thus reducing maintenance requirements, exhaust component contamination and allowing for a lowering of the particulates. The diluted NH3 is preferably supplied at approximately 200-500 SCCM, and the DCS flow rate is reduced to approximately 100-150 SCCM, at a pressure of approximately 200-350 mTorr.

摘要翻译： 本发明的实施例包括实现BARC层式炉沉积装置的提高的生产量的新装置和技术。 通过在BARC沉积工艺期间提供更高的NH 3流速来实现这一改进。 此外，这种改进可以通过将BARC层式炉沉积装置的温度梯度降低到约715-750℃来实现。例如，在氩气，氮气和氦气中的至少一种中约1-10％的NH 3共混物 被利用。 通过稀释NH 3，可以在炉沉积装置中使用更高的流速，从而允许增加BARC层厚度，折射率，消光系数和反射率特性的负载均匀性。 此外，由于稀释的NH 3的较高流速，NH 3耗尽减少并且优选地被消除。 此外，这种稀释的NH3允许减少DCS要求，从而减少维护要求，排气成分污染并允许降低颗粒物。 稀释的NH 3优选以约200-500SCCM供应，并且DCS流量在约200-350mTorr的压力下降低至约100-150SCCM。

公开(公告)号：US06475892B1

公开(公告)日：2002-11-05

申请号：US09365407

申请日：1999-08-02

申请人： Jayendra D. Bhakta

发明人： Jayendra D. Bhakta

IPC分类号： H01L2144

CPC分类号： H01L21/28017 ,  H01L21/28044 ,  H01L21/28123 ,  H01L21/32139

摘要： Polysilicon gates are formed with greater accuracy and consistency by depositing a silicon carbide antireflective layer on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon carbide layer in the same tool.

摘要翻译： 通过在图案化之前在多晶硅层上沉积碳化硅抗反射层，以更高的精度和一致性形成多晶硅栅极。 实施例还包括在同一工具中沉积多晶硅层和碳化硅层。

公开(公告)号：US6107167A

公开(公告)日：2000-08-22

申请号：US366216

申请日：1999-08-02

申请人： Jayendra D. Bhakta

发明人： Jayendra D. Bhakta

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/28035 ,  H01L21/28123 ,  H01L21/32139

摘要： Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer, e.g., amorphous silicon, on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the amorphous silicon layer in the same tool.

摘要翻译： 通过在图案化之前在多晶硅层上沉积抗反射层（例如非晶硅），以更高的精度和一致性形成多晶硅栅极。 实施例还包括在相同的工具中沉积多晶硅层和非晶硅层。

公开(公告)号：US06821883B1

公开(公告)日：2004-11-23

申请号：US10653848

申请日：2003-09-02

申请人： Carl P. Babcock ,  Jayendra D. Bhakta

发明人： Carl P. Babcock ,  Jayendra D. Bhakta

IPC分类号： H01L214763

CPC分类号： H01L21/76232

摘要： Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient >0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

摘要翻译： 通过初始形成具有组合消光系数> 0.5的多个光吸收层来提供晶体管和半导体衬底上的其它器件之间的浅沟槽隔离。 当反射光通过光吸收层时，大量的光被吸收到其中，从而阻挡这种反射光在光刻期间不利于光刻胶的图案化。 在光致抗蚀剂图案化之后，通过根据形成在光致抗蚀剂上的图案通过光吸收层蚀刻到半导体衬底中，在半导体衬底中形成隔离沟槽。

公开(公告)号：US06482573B1

公开(公告)日：2002-11-19

申请号：US09492216

申请日：2000-01-27

申请人： Jayendra D. Bhakta ,  Zicheng Gary Ling ,  Weizhong Wang ,  Warren T. Yu ,  Eric Kent

发明人： Jayendra D. Bhakta ,  Zicheng Gary Ling ,  Weizhong Wang ,  Warren T. Yu ,  Eric Kent

IPC分类号： G03C556

CPC分类号： G03F7/70625 ,  Y10S430/151

摘要： Critical dimension variation of photolithographically formed features on a semiconductor substrate is reduced by measuring the reflectivity of a photoresist layer and an underlying layer, such as a polysilicon layer, and adjusting the exposure level of the photoresist in accordance with the measured reflectivity. This allows precise control of feature width on the photoresist, which in turn allows precision etching of the underlying layer to accurately form a feature, such as a gate electrode.

摘要翻译： 通过测量光致抗蚀剂层和诸如多晶硅层的下层的反射率，并根据所测量的反射率来调整光致抗蚀剂的曝光水平，可减少半导体衬底上的光刻形成特征的临界尺寸变化。 这允许对光致抗蚀剂上的特征宽度的精确控制，这又允许精确地蚀刻下层以精确地形成特征，例如栅电极。