公开(公告)号：US06821883B1

公开(公告)日：2004-11-23

申请号：US10653848

申请日：2003-09-02

申请人： Carl P. Babcock ,  Jayendra D. Bhakta

发明人： Carl P. Babcock ,  Jayendra D. Bhakta

IPC分类号： H01L214763

CPC分类号： H01L21/76232

摘要： Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient >0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

摘要翻译： 通过初始形成具有组合消光系数> 0.5的多个光吸收层来提供晶体管和半导体衬底上的其它器件之间的浅沟槽隔离。 当反射光通过光吸收层时，大量的光被吸收到其中，从而阻挡这种反射光在光刻期间不利于光刻胶的图案化。 在光致抗蚀剂图案化之后，通过根据形成在光致抗蚀剂上的图案通过光吸收层蚀刻到半导体衬底中，在半导体衬底中形成隔离沟槽。

公开(公告)号：US06645868B1

公开(公告)日：2003-11-11

申请号：US09861990

申请日：2001-05-17

申请人： Carl P. Babcock ,  Jayendra D. Bhakta

发明人： Carl P. Babcock ,  Jayendra D. Bhakta

IPC分类号： H01L21762

CPC分类号： H01L21/76232 ,  Y10S438/95 ,  Y10S438/952

摘要： Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

摘要翻译： 通过最初形成一层高吸收富硅氮化物以在半导体衬底和光致抗蚀剂之间用作硬掩模，来提供晶体管和半导体衬底上的其它器件之间的浅沟槽隔离。 富含氮化物的高吸收层的消光系数（k）> 0.5。 当反射光穿过富含硅的氮化物层时，基本上量的光被吸收在其中，从而阻止这种反射光在光刻期间不利于光刻胶的图案化。 在光致抗蚀剂图案化之后，通过根据形成在光致抗蚀剂上的图案通过富硅氮化物进行蚀刻，在半导体衬底中形成隔离沟槽。

公开(公告)号：US07061075B1

公开(公告)日：2006-06-13

申请号：US10972870

申请日：2004-10-25

申请人： Carl P. Babcock ,  Jayendra D. Bhakta

发明人： Carl P. Babcock ,  Jayendra D. Bhakta

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A film stack for forming shallow trench isolation among transistors and other devices on a semiconductor substrate is provided, including a plurality of light absorbing layers alternating between a layer of SiON and a layer of SiO2 and having a combined extinction coefficient >0.5. As reflected light interacts with the light absorbing layers, a substantial amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches may be formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

摘要翻译： 提供了一种用于在半导体衬底上的晶体管和其它器件之间形成浅沟槽隔离的膜叠层，包括在SiON层和SiO 2层之间交替的多个光吸收层，并且具有组合 消光系数> 0.5。 当反射光与光吸收层相互作用时，大量的光被吸收到其中，由此阻挡这种反射光，从而在光刻期间阻碍光刻胶的图案化。 在光致抗蚀剂图案化之后，可以根据形成在光致抗蚀剂上的图案，通过光吸收层蚀刻到半导体衬底中，在半导体衬底中形成隔离沟槽。

公开(公告)号：US06335235B1

公开(公告)日：2002-01-01

申请号：US09376055

申请日：1999-08-17

申请人： Jayendra D. Bhakta ,  Carl P. Babcock

发明人： Jayendra D. Bhakta ,  Carl P. Babcock

IPC分类号： H01L218238

CPC分类号： H01L21/76229

摘要： Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.

摘要翻译： 通过在图案化之前在氮化硅层上形成氧化物 - 氮化硅堆叠，然后沉积非晶硅抗反射层，形成更高的精度和一致性的隔离区域。 实施例还包括在相同的工具中沉积氮化硅层和非晶硅层。

公开(公告)号：US06255717B1

公开(公告)日：2001-07-03

申请号：US09200307

申请日：1998-11-25

申请人： Carl P. Babcock ,  Jayendra D. Bhakta

发明人： Carl P. Babcock ,  Jayendra D. Bhakta

IPC分类号： H01L2358

CPC分类号： H01L21/76232 ,  Y10S438/95 ,  Y10S438/952

摘要： Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photolithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

摘要翻译： 通过最初形成一层高吸收富硅氮化物以在半导体衬底和光致抗蚀剂之间用作硬掩模，来提供晶体管和半导体衬底上的其它器件之间的浅沟槽隔离。 富含氮化物的高吸收层的消光系数（k）> 0.5。 当反射光穿过富含硅的氮化物层时，基本上量的光被吸收在其中，从而在光刻期间阻挡这种反射光对光致抗蚀剂的图案化产生负面干扰。 在光致抗蚀剂图案化之后，通过根据形成在光致抗蚀剂上的图案通过富硅氮化物进行蚀刻，在半导体衬底中形成隔离沟槽。

公开(公告)号：US07422829B1

公开(公告)日：2008-09-09

申请号：US10859276

申请日：2004-06-02

申请人： Carl P. Babcock ,  Jongwook Kye

发明人： Carl P. Babcock ,  Jongwook Kye

IPC分类号： G03F1/00 ,  G06F17/20

CPC分类号： G03F7/70625 ,  G03F1/36 ,  G03F1/70

摘要： A method of adjusting a reticle layout to correct for flare can include determining a localized reticle pattern density across the reticle layout and determining a relationship between reticle pattern density and edge adjustment for the photolithography apparatus being used. For a given feature of the reticle layout, an edge of the feature can be adjusted by a given amount based on the localized reticle pattern density adjacent the given feature. This method allows for a rule-based optical proximity correction (OPC) approach to compensate for long-range and short-range flare within a photolithography apparatus.

摘要翻译： 调整掩模版布局以校正火炬的方法可以包括确定横跨标线布局的局部掩模图案密度，并确定所使用的光刻设备的掩模版图案密度和边缘调整之间的关系。 对于标线布局的给定特征，可以基于与给定特征相邻的局部掩模版图案密度，将特征的边缘调整给定量。 该方法允许基于规则的光学邻近校正（OPC）方法来补偿光刻设备内的远距离和短距离闪光。

公开(公告)号：US07269804B2

公开(公告)日：2007-09-11

申请号：US10816764

申请日：2004-04-02

申请人： Cyrus E. Tabery ,  Todd P. Lukanc ,  Chris Haidinyak ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

发明人： Cyrus E. Tabery ,  Todd P. Lukanc ,  Chris Haidinyak ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

IPC分类号： G06F17/50

CPC分类号： G03F7/70433 ,  G03F7/705

摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

摘要翻译： 选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。 对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。 可以选择提供最佳可制造性的RET。 以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

公开(公告)号：US06423555B1

公开(公告)日：2002-07-23

申请号：US09633441

申请日：2000-08-07

申请人： Carl P. Babcock

发明人： Carl P. Babcock

IPC分类号： G01R3126

CPC分类号： H01L22/12

摘要： A method of inspecting a semiconductive wafer-in-process to determine the accuracy of alignment of a lower process layer to an upper process layer. In this method, a conductive target attribute is formed on a first alignment portion of the wafer-in-process. A contact attribute is formed on the upper process layer through which an electric path can be established with the target attribute in an acceptable alignment situation but cannot established in an unacceptable alignment situation. By attempting to establish an electric path from the target attribute through the contact attribute, the accuracy of alignment can be determined based on whether or not an electrical path is established. The target attribute may be a series of conductive strips and the contact attribute may be a series of contact holes that will overlay the corresponding target attributes in differing degrees in an acceptable alignment situation. The overlay arrangement may be such that the magnitude and/or direction of misalignment may be determined by the electrical path arrangement that is established during the inspection process.

摘要翻译： 检查半导体晶片在工艺中以确定下工艺层与上工艺层的对准精度的方法。 在该方法中，在处理晶片的第一对准部分上形成导电目标属性。 在上层处理层上形成接触属性，通过该接触属性可以以可接受的对准情况与目标属性建立电路径，但不能在不可接受的对准情况下建立接触属性。 通过尝试通过接触属性从目标属性建立电路径，可以基于电路是否建立来确定对准精度。 目标属性可以是一系列导电条，并且接触属性可以是一系列接触孔，其将以可接受的对准情况以不同程度覆盖相应的目标属性。 覆盖布置可以使得不对准的大小和/或方向可以由检查过程中建立的电路布置来确定。

公开(公告)号：US07207017B1

公开(公告)日：2007-04-17

申请号：US10865047

申请日：2004-06-10

申请人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

发明人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

摘要翻译： 生成计量配方的方法包括识别设备布局内的感兴趣区域。 可以提供对应于所识别的感兴趣区域的坐标列表并用于创建剪切布局，其可以由剪切布局数据文件表示。 裁剪的布局数据文件和相应的坐标列表可以被提供并转换成用于在测试处理的晶片和/或掩模版时引导一个或多个计量仪器的计量配方。 根据测量要求收到的实验测量结果可以与相应的设计数据和仿真数据相关联，并存储在可数据库系统中。

公开(公告)号：US06358843B1

公开(公告)日：2002-03-19

申请号：US09824421

申请日：2001-04-02

申请人： Carl P. Babcock ,  Bhanwar Singh

发明人： Carl P. Babcock ,  Bhanwar Singh

IPC分类号： H01L214763

CPC分类号： G03F7/203 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76802

摘要： A method of fabricating ultra small vias in insulating layers on a semiconductor substrate for an integrated circuit by a first exposure of a photoresist to line pattern with the semiconductor substrate in a first position and the exposure dosage being insufficient to develop the photoresist followed by a second overlapping exposure of the line pattern with the semiconductor substrate being in a position 90° from the first position and again being insufficient in exposure dosage to develop the photoresist, the overlapped line exposures creating via exposures of sufficient dosage to develop the photoresist, thereby creating a smaller via opening than with a single exposure.

摘要翻译： 一种在半导体衬底上用于集成电路的绝缘层中的超小通孔的制造方法，该方法是通过在第一位置首先将半导体衬底的光致抗蚀剂曝光到线图案，并且曝光剂量不足以显影光致抗蚀剂，然后是第二 线路图案与半导体衬底的重叠曝光处于距离第一位置90°的位置，并且曝光用量不足以显影光致抗蚀剂，通过曝光足够的剂量产生重叠的线暴露以显影光致抗蚀剂，由此产生 通过开口比单次曝光更小。